Fix gearing

[gram.git] / gram / compat.py

diff --git a/gram/compat.py b/gram/compat.py
index 5bda03175d5e0064ede6d62be1cb7c8f5cabb9bc..49ae71013312da80091197c800e51b072b916aa4 100644 (file)
--- a/gram/compat.py
+++ b/gram/compat.py
@@ -27,49 +27,6 @@ def delayed_enter(m, src, dst, delay):
         with m.State(statename):
             m.next = deststate
 
-class DelayedEnterTestCase(unittest.TestCase):
-    def test_sequence(self):
-        def sequence(expected_delay):
-            m = Module()
-
-            before = Signal()
-            end = Signal()
-
-            with m.FSM():
-                with m.State("Before-Delayed-Enter"):
-                    m.d.comb += before.eq(1)
-                    m.next = "Delayed-Enter"
-
-                delayed_enter(m, "Delayed-Enter", "End-Delayed-Enter", expected_delay)
-
-                with m.State("End-Delayed-Enter"):
-                    m.d.comb += end.eq(1)
-
-            def process():
-                while (yield before):
-                    yield
-
-                delay = 0
-                while not (yield end):
-                    yield
-                    delay += 1
-
-                self.assertEqual(delay, expected_delay)
-
-            sim = Simulator(m)
-            with sim.write_vcd("test_compat.vcd"):
-                sim.add_clock(1e-6)
-                sim.add_sync_process(process)
-                sim.run()
-
-        with self.assertRaises(AssertionError):
-            sequence(0)
-        sequence(1)
-        sequence(2)
-        sequence(10)
-        sequence(100)
-        sequence(1000)
-
 class RoundRobin(Elaboratable):
     """A round-robin scheduler. (HarryHo90sHK)
     Parameters
@@ -95,16 +52,19 @@ class RoundRobin(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        with m.If(self.stb):
-            with m.Switch(self.grant):
-                for i in range(self.n):
-                    with m.Case(i):
-                        for j in reversed(range(i+1, i+self.n)):
-                            # If i+1 <= j < n, then t == j;     (after i)
-                            # If n <= j < i+n, then t == j - n  (before i)
-                            t = j % self.n
-                            with m.If(self.request[t]):
-                                m.d.sync += self.grant.eq(t)
+        if self.n == 1:
+            m.d.comb += self.grant.eq(0)
+        else:
+            with m.If(self.stb):
+                with m.Switch(self.grant):
+                    for i in range(self.n):
+                        with m.Case(i):
+                            for j in reversed(range(i+1, i+self.n)):
+                                # If i+1 <= j < n, then t == j;     (after i)
+                                # If n <= j < i+n, then t == j - n  (before i)
+                                t = j % self.n
+                                with m.If(self.request[t]):
+                                    m.d.sync += self.grant.eq(t)
 
         return m
 
@@ -146,67 +106,6 @@ class Timeline(Elaboratable):
 
         return m
 
-class TimelineTestCase(unittest.TestCase):
-    def test_sequence(self):
-        sigA = Signal()
-        sigB = Signal()
-        sigC = Signal()
-        timeline = Timeline([
-            (1, sigA.eq(1)),
-            (5, sigA.eq(1)),
-            (7, sigA.eq(0)),
-            (10, sigB.eq(1)),
-            (11, sigB.eq(0)),
-        ])
-        m = Module()
-        m.submodules.timeline = timeline
-
-        def process():
-            # Test default value for unset signals
-            self.assertFalse((yield sigA))
-            self.assertFalse((yield sigB))
-
-            # Ensure that the sequence isn't triggered without the trigger signal
-            for i in range(100):
-                yield
-                self.assertFalse((yield sigA))
-                self.assertFalse((yield sigB))
-
-            yield timeline.trigger.eq(1)
-            yield
-            yield timeline.trigger.eq(0)
-
-            for i in range(11+1):
-                yield
-
-                if i == 1:
-                    self.assertTrue((yield sigA))
-                    self.assertFalse((yield sigB))
-                elif i == 5:
-                    self.assertTrue((yield sigA))
-                    self.assertFalse((yield sigB))
-                elif i == 7:
-                    self.assertFalse((yield sigA))
-                    self.assertFalse((yield sigB))
-                elif i == 10:
-                    self.assertFalse((yield sigA))
-                    self.assertTrue((yield sigB))
-                elif i == 11:
-                    self.assertFalse((yield sigA))
-                    self.assertFalse((yield sigB))
-
-            # Ensure no changes happen once the sequence is done
-            for i in range(100):
-                yield
-                self.assertFalse((yield sigA))
-                self.assertFalse((yield sigB))
-
-        sim = Simulator(m)
-        with sim.write_vcd("test_compat.vcd"):
-            sim.add_clock(1e-6)
-            sim.add_sync_process(process)
-            sim.run()
-
 
 class CSRPrefixProxy:
     def __init__(self, bank, prefix):