with m.State(statename):
m.next = deststate
-# Original nMigen implementation by HarryHo90sHK
-
-
class RoundRobin(Elaboratable):
- """A round-robin scheduler.
+ """A round-robin scheduler. (HarryHo90sHK)
Parameters
----------
n : int
def elaborate(self, platform):
m = Module()
- with m.If(self.stb):
- with m.Switch(self.grant):
- for i in range(self.n):
- with m.Case(i):
- for j in reversed(range(i+1, i+self.n)):
- # If i+1 <= j < n, then t == j; (after i)
- # If n <= j < i+n, then t == j - n (before i)
- t = j % self.n
- with m.If(self.request[t]):
- m.d.sync += self.grant.eq(t)
+ if self.n == 1:
+ m.d.comb += self.grant.eq(0)
+ else:
+ with m.If(self.stb):
+ with m.Switch(self.grant):
+ for i in range(self.n):
+ with m.Case(i):
+ for j in reversed(range(i+1, i+self.n)):
+ # If i+1 <= j < n, then t == j; (after i)
+ # If n <= j < i+n, then t == j - n (before i)
+ t = j % self.n
+ with m.If(self.request[t]):
+ m.d.sync += self.grant.eq(t)
return m
return m
-class TimelineTestCase(unittest.TestCase):
- def test_sequence(self):
- sigA = Signal()
- sigB = Signal()
- sigC = Signal()
- timeline = Timeline([
- (1, sigA.eq(1)),
- (5, sigA.eq(1)),
- (7, sigA.eq(0)),
- (10, sigB.eq(1)),
- (11, sigB.eq(0)),
- ])
- m = Module()
- m.submodules.timeline = timeline
-
- def process():
- # Test default value for unset signals
- self.assertFalse((yield sigA))
- self.assertFalse((yield sigB))
-
- # Ensure that the sequence isn't triggered without the trigger signal
- for i in range(100):
- yield
- self.assertFalse((yield sigA))
- self.assertFalse((yield sigB))
-
- yield timeline.trigger.eq(1)
- yield
-
- for i in range(11+1):
- yield
-
- if i == 1:
- self.assertTrue((yield sigA))
- self.assertFalse((yield sigB))
- elif i == 5:
- self.assertTrue((yield sigA))
- self.assertFalse((yield sigB))
- elif i == 7:
- self.assertFalse((yield sigA))
- self.assertFalse((yield sigB))
- elif i == 10:
- self.assertFalse((yield sigA))
- self.assertTrue((yield sigB))
- elif i == 11:
- self.assertFalse((yield sigA))
- self.assertFalse((yield sigB))
-
- sim = Simulator(m)
- with sim.write_vcd("test_compat.vcd"):
- sim.add_clock(1e-6)
- sim.add_sync_process(process)
- sim.run()
-
class CSRPrefixProxy:
def __init__(self, bank, prefix):