Add more memory tests

[gram.git] / gram / dfii.py

diff --git a/gram/dfii.py b/gram/dfii.py
index 34d85bc3ca100411f7c7b1208542547f367f80f3..5b9664cca4076785db138103f13f25d1f50e7e81 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -61,14 +61,11 @@ class DFIInjector(Elaboratable):
     def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
         self._nranks = nranks
 
-        self._inti = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
-        self.slave = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
-        self.master = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
+        self._inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
 
-        self._control = csr_bank.csr(4, "w")  # sel, cke, odt, reset_n
+        self._control = csr_bank.csr(4, "w")  # sel, clk_en, odt, reset_n
 
         self._phases = []
         for n, phase in enumerate(self._inti.phases):
@@ -86,7 +83,7 @@ class DFIInjector(Elaboratable):
             m.d.comb += self._inti.connect(self.master)
 
         for i in range(self._nranks):
-            m.d.comb += [phase.cke[i].eq(self._control.w_data[1])
+            m.d.comb += [phase.clk_en[i].eq(self._control.w_data[1])
                          for phase in self._inti.phases]
             m.d.comb += [phase.odt[i].eq(self._control.w_data[2])
                          for phase in self._inti.phases if hasattr(phase, "odt")]