Fix memtest tests (missing parenthesis)

[gram.git] / gram / dfii.py

diff --git a/gram/dfii.py b/gram/dfii.py
index 3436e33a92c02b3509238ce3fde421f20b0ea214..5b9664cca4076785db138103f13f25d1f50e7e81 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -6,21 +6,19 @@
 from nmigen import *
 
 from gram.phy import dfi
-from lambdasoc.periph import Peripheral
+from gram.compat import CSRPrefixProxy
 
 # PhaseInjector ------------------------------------------------------------------------------------
 
-class PhaseInjector(Peripheral, Elaboratable):
-    def __init__(self, phase):
-        super().__init__(name = "phaseinjector")
 
-        bank = self.csr_bank()
-        self._command = bank.csr(6, "rw")
-        self._command_issue = bank.csr(1, "rw")
-        self._address = bank.csr(len(phase.address), "rw")
-        self._baddress = bank.csr(len(phase.bank), "rw")
-        self._wrdata = bank.csr(len(phase.wrdata), "rw")
-        self._rddata = bank.csr(len(phase.rddata), "rw")
+class PhaseInjector(Elaboratable):
+    def __init__(self, csr_bank, phase):
+        self._command = csr_bank.csr(6, "w")
+        self._command_issue = csr_bank.csr(1, "w")
+        self._address = csr_bank.csr(len(phase.address), "w")
+        self._baddress = csr_bank.csr(len(phase.bank), "w")
+        self._wrdata = csr_bank.csr(len(phase.wrdata), "w")
+        self._rddata = csr_bank.csr(len(phase.rddata), "r")
 
         self._phase = phase
 
@@ -28,20 +26,20 @@ class PhaseInjector(Peripheral, Elaboratable):
         m = Module()
 
         m.d.comb += [
-            self._phase.address.eq(self._address.r_data),
-            self._phase.bank.eq(self._baddress.r_data),
-            self._phase.wrdata_en.eq(self._command_issue.r_stb & self._command.r_data[4]),
-            self._phase.rddata_en.eq(self._command_issue.r_stb & self._command.r_data[5]),
-            self._phase.wrdata.eq(self._wrdata.r_data),
+            self._phase.address.eq(self._address.w_data),
+            self._phase.bank.eq(self._baddress.w_data),
+            self._phase.wrdata_en.eq(self._command_issue.w_stb & self._command.w_data[4]),
+            self._phase.rddata_en.eq(self._command_issue.w_stb & self._command.w_data[5]),
+            self._phase.wrdata.eq(self._wrdata.w_data),
             self._phase.wrdata_mask.eq(0)
         ]
 
-        with m.If(self._command_issue.r_stb):
+        with m.If(self._command_issue.w_stb):
             m.d.comb += [
-                self._phase.cs_n.eq(Repl(value=~self._command.r_data[0], count=len(self._phase.cs_n))),
-                self._phase.we_n.eq(~self._command.r_data[1]),
-                self._phase.cas_n.eq(~self._command.r_data[2]),
-                self._phase.ras_n.eq(~self._command.r_data[3]),
+                self._phase.cs_n.eq(Repl(value=~self._command.w_data[0], count=len(self._phase.cs_n))),
+                self._phase.we_n.eq(~self._command.w_data[1]),
+                self._phase.cas_n.eq(~self._command.w_data[2]),
+                self._phase.ras_n.eq(~self._command.w_data[3]),
             ]
         with m.Else():
             m.d.comb += [
@@ -52,39 +50,44 @@ class PhaseInjector(Peripheral, Elaboratable):
             ]
 
         with m.If(self._phase.rddata_valid):
-            m.d.sync += self._rddata.w_data.eq(self._phase.rddata)
+            m.d.sync += self._rddata.r_data.eq(self._phase.rddata)
 
         return m
 
 # DFIInjector --------------------------------------------------------------------------------------
 
-class DFIInjector(Peripheral, Elaboratable):
-    def __init__(self, addressbits, bankbits, nranks, databits, nphases=1):
-        super().__init__(name = "dfii")
 
+class DFIInjector(Elaboratable):
+    def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
         self._nranks = nranks
 
-        self._inti  = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
-        self.slave  = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self._inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
         self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
 
-        bank = self.csr_bank()
-        self._control = bank.csr(4, "rw")  # sel, cke, odt, reset_n
+        self._control = csr_bank.csr(4, "w")  # sel, clk_en, odt, reset_n
+
+        self._phases = []
+        for n, phase in enumerate(self._inti.phases):
+            self._phases += [PhaseInjector(CSRPrefixProxy(csr_bank,
+                                                          "p{}".format(n)), phase)]
 
     def elaborate(self, platform):
         m = Module()
 
-        for n, phase in enumerate(self._inti.phases):
-            setattr(m.submodules, "pi" + str(n), PhaseInjector(phase))
+        m.submodules += self._phases
 
-        with m.If(self._control.r_data[0]):
+        with m.If(self._control.w_data[0]):
             m.d.comb += self.slave.connect(self.master)
         with m.Else():
             m.d.comb += self._inti.connect(self.master)
 
         for i in range(self._nranks):
-            m.d.comb += [phase.cke[i].eq(self._control.r_data[1]) for phase in self._inti.phases]
-            m.d.comb += [phase.odt[i].eq(self._control.r_data[2]) for phase in self._inti.phases if hasattr(phase, "odt")]
-        m.d.comb += [phase.reset_n.eq(self._control.r_data[3]) for phase in self._inti.phases if hasattr(phase, "reset_n")]
+            m.d.comb += [phase.clk_en[i].eq(self._control.w_data[1])
+                         for phase in self._inti.phases]
+            m.d.comb += [phase.odt[i].eq(self._control.w_data[2])
+                         for phase in self._inti.phases if hasattr(phase, "odt")]
+        m.d.comb += [phase.reset_n.eq(self._control.w_data[3])
+                     for phase in self._inti.phases if hasattr(phase, "reset_n")]
 
         return m