Update switch to nMigen syntax

[gram.git] / gram / phy / ecp5ddrphy.py

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index cf1a9c93ac3888defd72f610b7ea8c57783c41a1..9a3818d6bfb0734dfdb61f97491e3d7568478e2b 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -43,7 +43,7 @@ class ECP5DDRPHYInit(Elaboratable):
         _lock = Signal()
         delay = Signal()
         m.submodules += Instance("DDRDLLA",
-                                 i_CLK=ClockSignal("sys2x"),
+                                 i_CLK=ClockSignal("sync2x"),
                                  i_RST=ResetSignal(),
                                  i_UDDCNTLN=~update,
                                  i_FREEZE=freeze,
@@ -120,13 +120,13 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         addressbits = len(self.pads.a.o)
         bankbits = len(self.pads.ba.o)
         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n)
-        databits = len(self.pads.dq.oe)
+        databits = len(self.pads.dq.o)
         self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
 
         # PHY settings -----------------------------------------------------------------------------
         tck = 2/(2*2*self._sys_clk_freq)
         nphases = 2
-        databits = len(self.pads.dq.oe)
+        databits = len(self.pads.dq.o)
         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n)
         addressbits = len(self.pads.a.o)
         bankbits = len(self.pads.ba.o)
@@ -159,13 +159,13 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
 
         tck = 2/(2*2*self._sys_clk_freq)
         nphases = 2
-        databits = len(self.pads.dq.oe)
+        databits = len(self.pads.dq.o)
         nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n)
         addressbits = len(self.pads.a.o)
         bankbits = len(self.pads.ba.o)
 
         # Init -------------------------------------------------------------------------------------
-        m.submodules.init = DomainRenamer("init")(ECP5DDRPHYInit("sys2x"))
+        m.submodules.init = DomainRenamer("init")(ECP5DDRPHYInit("sync2x"))
 
         # Parameters -------------------------------------------------------------------------------
         cl, cwl = get_cl_cw("DDR3", tck)
@@ -185,8 +185,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         for i in range(len(self.pads.clk.o)):
             sd_clk_se = Signal()
             m.submodules += Instance("ODDRX2F",
-                                     i_RST=ResetSignal("sys2x"),
-                                     i_ECLK=ClockSignal("sys2x"),
+                                     i_RST=ResetSignal("sync2x"),
+                                     i_ECLK=ClockSignal("sync2x"),
                                      i_SCLK=ClockSignal(),
                                      i_D0=0,
                                      i_D1=1,
@@ -198,8 +198,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         # Addresses and Commands ---------------------------------------------------------------
         for i in range(addressbits):
             m.submodules += Instance("ODDRX2F",
-                                     i_RST=ResetSignal("sys2x"),
-                                     i_ECLK=ClockSignal("sys2x"),
+                                     i_RST=ResetSignal("sync2x"),
+                                     i_ECLK=ClockSignal("sync2x"),
                                      i_SCLK=ClockSignal(),
                                      i_D0=dfi.phases[0].address[i],
                                      i_D1=dfi.phases[0].address[i],
@@ -209,8 +209,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                                      )
         for i in range(bankbits):
             m.submodules += Instance("ODDRX2F",
-                                     i_RST=ResetSignal("sys2x"),
-                                     i_ECLK=ClockSignal("sys2x"),
+                                     i_RST=ResetSignal("sync2x"),
+                                     i_ECLK=ClockSignal("sync2x"),
                                      i_SCLK=ClockSignal(),
                                      i_D0=dfi.phases[0].bank[i],
                                      i_D1=dfi.phases[0].bank[i],
@@ -226,8 +226,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         for name in controls:
             for i in range(len(getattr(self.pads, name))):
                 m.submodules += Instance("ODDRX2F",
-                                         i_RST=ResetSignal("sys2x"),
-                                         i_ECLK=ClockSignal("sys2x"),
+                                         i_RST=ResetSignal("sync2x"),
+                                         i_ECLK=ClockSignal("sync2x"),
                                          i_SCLK=ClockSignal(),
                                          i_D0=getattr(dfi.phases[0], name)[i],
                                          i_D1=getattr(dfi.phases[0], name)[i],
@@ -250,36 +250,36 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             rdpntr = Signal(3)
             wrpntr = Signal(3)
             rdly = Signal(7)
-            with m.If(self._dly_sel.storage[i]):
-                with m.If(self._rdly_dq_rst.re):
+            with m.If(self._dly_sel.w_data[i]):
+                with m.If(self._rdly_dq_rst.w_stb):
                     m.d.sync += rdly.eq(0)
-                with m.Elif(self._rdly_dq_inc.re):
+                with m.Elif(self._rdly_dq_inc.w_stb):
                     m.d.sync += rdly.eq(rdly + 1)
             datavalid = Signal()
             burstdet = Signal()
             dqs_read = Signal()
             dqs_bitslip = Signal(2)
-            with m.If(self._dly_sel.storage[i]):
-                with m.If(self._rdly_dq_bitslip_rst.re):
+            with m.If(self._dly_sel.w_data[i]):
+                with m.If(self._rdly_dq_bitslip_rst.w_stb):
                     m.d.sync += dqs_bitslip.eq(0)
-                with m.Elif(self._rdly_dq_bitslip.re):
+                with m.Elif(self._rdly_dq_bitslip.w_stb):
                     m.d.sync += dqs_bitslip.eq(dqs_bitslip + 1)
-            dqs_cases = {}
-            for j, b in enumerate(range(-2, 2)):
-                dqs_cases[j] = dqs_read.eq(
-                    rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0)
-            m.d.sync += Case(dqs_bitslip, dqs_cases)
+            with m.Switch(dqs_bitslip):
+                for j, b in enumerate(range(-2, 2)):
+                    with m.Case(j):
+                        m.d.sync += dqs_read.eq(rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0)
+
             m.submodules += Instance("DQSBUFM",
                                      p_DQS_LI_DEL_ADJ="MINUS",
                                      p_DQS_LI_DEL_VAL=1,
                                      p_DQS_LO_DEL_ADJ="MINUS",
                                      p_DQS_LO_DEL_VAL=4,
                                      # Clocks / Reset
-                                     i_SCLK=ClockSignal("sys"),
-                                     i_ECLK=ClockSignal("sys2x"),
-                                     i_RST=ResetSignal("sys2x"),
+                                     i_SCLK=ClockSignal("sync"),
+                                     i_ECLK=ClockSignal("sync2x"),
+                                     i_RST=ResetSignal("sync2x"),
                                      i_DDRDEL=self.init.delay,
-                                     i_PAUSE=self.init.pause | self._dly_sel.storage[i],
+                                     i_PAUSE=self.init.pause | self._dly_sel.w_data[i],
 
                                      # Control
                                      # Assert LOADNs to use DDRDEL control
@@ -313,7 +313,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                                      )
             burstdet_d = Signal()
             m.d.sync += burstdet_d.eq(burstdet)
-            with m.If(self._burstdet_clr.re):
+            with m.If(self._burstdet_clr.w_stb):
                 m.d.sync += self._burstdet_seen.status[i].eq(0)
             with m.If(burstdet & ~burstdet_d):
                 m.d.sync += self._burstdet_seen.status[i].eq(1)
@@ -339,8 +339,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             dm_bl8_cases[1] = dm_o_data_muxed.eq(dm_o_data_d[4:])
             m.d.sync += Case(bl8_chunk, dm_bl8_cases)  # FIXME: use self.comb?
             m.submodules += Instance("ODDRX2DQA",
-                                     i_RST=ResetSignal("sys2x"),
-                                     i_ECLK=ClockSignal("sys2x"),
+                                     i_RST=ResetSignal("sync2x"),
+                                     i_ECLK=ClockSignal("sync2x"),
                                      i_SCLK=ClockSignal(),
                                      i_DQSW270=dqsw270,
                                      i_D0=dm_o_data_muxed[0],
@@ -354,8 +354,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             dqs_oe_n = Signal()
             m.submodules += [
                 Instance("ODDRX2DQSB",
-                         i_RST=ResetSignal("sys2x"),
-                         i_ECLK=ClockSignal("sys2x"),
+                         i_RST=ResetSignal("sync2x"),
+                         i_ECLK=ClockSignal("sync2x"),
                          i_SCLK=ClockSignal(),
                          i_DQSW=dqsw,
                          i_D0=0,  # FIXME: dqs_pattern.o[3],
@@ -365,8 +365,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                          o_Q=dqs
                          ),
                 Instance("TSHX2DQSA",
-                         i_RST=ResetSignal("sys2x"),
-                         i_ECLK=ClockSignal("sys2x"),
+                         i_RST=ResetSignal("sync2x"),
+                         i_ECLK=ClockSignal("sync2x"),
                          i_SCLK=ClockSignal(),
                          i_DQSW=dqsw,
                          i_T0=~(dqs_pattern.preamble | dqs_oe |
@@ -407,8 +407,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                 _dq_i_data = Signal(4)
                 m.submodules += [
                     Instance("ODDRX2DQA",
-                             i_RST=ResetSignal("sys2x"),
-                             i_ECLK=ClockSignal("sys2x"),
+                             i_RST=ResetSignal("sync2x"),
+                             i_ECLK=ClockSignal("sync2x"),
                              i_SCLK=ClockSignal(),
                              i_DQSW270=dqsw270,
                              i_D0=dq_o_data_muxed[0],
@@ -426,8 +426,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                              o_Z=dq_i_delayed
                              ),
                     Instance("IDDRX2DQA",
-                             i_RST=ResetSignal("sys2x"),
-                             i_ECLK=ClockSignal("sys2x"),
+                             i_RST=ResetSignal("sync2x"),
+                             i_ECLK=ClockSignal("sync2x"),
                              i_SCLK=ClockSignal(),
                              i_DQSR90=dqsr90,
                              i_RDPNTR0=rdpntr[0],
@@ -457,8 +457,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                 ]
                 m.submodules += [
                     Instance("TSHX2DQA",
-                             i_RST=ResetSignal("sys2x"),
-                             i_ECLK=ClockSignal("sys2x"),
+                             i_RST=ResetSignal("sync2x"),
+                             i_ECLK=ClockSignal("sync2x"),
                              i_SCLK=ClockSignal(),
                              i_DQSW270=dqsw270,
                              i_T0=~(dqs_pattern.preamble | dq_oe |