addressbits = len(self.pads.a.o)
bankbits = len(self.pads.ba.o)
nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n)
- databits = len(self.pads.dq.oe)
+ databits = len(self.pads.dq.o)
self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
# PHY settings -----------------------------------------------------------------------------
tck = 2/(2*2*self._sys_clk_freq)
nphases = 2
- databits = len(self.pads.dq.oe)
+ databits = len(self.pads.dq.o)
nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n)
addressbits = len(self.pads.a.o)
bankbits = len(self.pads.ba.o)
tck = 2/(2*2*self._sys_clk_freq)
nphases = 2
- databits = len(self.pads.dq.oe)
+ databits = len(self.pads.dq.o)
nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n)
addressbits = len(self.pads.a.o)
bankbits = len(self.pads.ba.o)
# Init -------------------------------------------------------------------------------------
- m.submodules.init = DomainRenamer("init")(ECP5DDRPHYInit("sync2x"))
+ m.submodules.init = init = DomainRenamer("init")(ECP5DDRPHYInit("sync2x"))
# Parameters -------------------------------------------------------------------------------
cl, cwl = get_cl_cw("DDR3", tck)
rdpntr = Signal(3)
wrpntr = Signal(3)
rdly = Signal(7)
- with m.If(self._dly_sel.storage[i]):
- with m.If(self._rdly_dq_rst.re):
+ with m.If(self._dly_sel.w_data[i]):
+ with m.If(self._rdly_dq_rst.w_stb):
m.d.sync += rdly.eq(0)
- with m.Elif(self._rdly_dq_inc.re):
+ with m.Elif(self._rdly_dq_inc.w_stb):
m.d.sync += rdly.eq(rdly + 1)
datavalid = Signal()
burstdet = Signal()
dqs_read = Signal()
dqs_bitslip = Signal(2)
- with m.If(self._dly_sel.storage[i]):
- with m.If(self._rdly_dq_bitslip_rst.re):
+ with m.If(self._dly_sel.w_data[i]):
+ with m.If(self._rdly_dq_bitslip_rst.w_stb):
m.d.sync += dqs_bitslip.eq(0)
- with m.Elif(self._rdly_dq_bitslip.re):
+ with m.Elif(self._rdly_dq_bitslip.w_stb):
m.d.sync += dqs_bitslip.eq(dqs_bitslip + 1)
- dqs_cases = {}
- for j, b in enumerate(range(-2, 2)):
- dqs_cases[j] = dqs_read.eq(
- rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0)
- m.d.sync += Case(dqs_bitslip, dqs_cases)
+ with m.Switch(dqs_bitslip):
+ for j, b in enumerate(range(-2, 2)):
+ with m.Case(j):
+ m.d.sync += dqs_read.eq(rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0)
+
m.submodules += Instance("DQSBUFM",
p_DQS_LI_DEL_ADJ="MINUS",
p_DQS_LI_DEL_VAL=1,
p_DQS_LO_DEL_ADJ="MINUS",
p_DQS_LO_DEL_VAL=4,
# Clocks / Reset
- i_SCLK=ClockSignal("sys"),
+ i_SCLK=ClockSignal("sync"),
i_ECLK=ClockSignal("sync2x"),
i_RST=ResetSignal("sync2x"),
- i_DDRDEL=self.init.delay,
- i_PAUSE=self.init.pause | self._dly_sel.storage[i],
+ i_DDRDEL=init.delay,
+ i_PAUSE=init.pause | self._dly_sel.w_data[i],
# Control
# Assert LOADNs to use DDRDEL control
)
burstdet_d = Signal()
m.d.sync += burstdet_d.eq(burstdet)
- with m.If(self._burstdet_clr.re):
- m.d.sync += self._burstdet_seen.status[i].eq(0)
+ with m.If(self._burstdet_clr.w_stb):
+ m.d.sync += self._burstdet_seen.r_data[i].eq(0)
with m.If(burstdet & ~burstdet_d):
- m.d.sync += self._burstdet_seen.status[i].eq(1)
+ m.d.sync += self._burstdet_seen.r_data[i].eq(1)
# DQS and DM ---------------------------------------------------------------------------
dm_o_data = Signal(8)