Fix old CSRStatus code

[gram.git] / gram / phy / ecp5ddrphy.py

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 9a3818d6bfb0734dfdb61f97491e3d7568478e2b..fb54126219d3354f1fd0e3c4a3842bb28ad91419 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -165,7 +165,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         bankbits = len(self.pads.ba.o)
 
         # Init -------------------------------------------------------------------------------------
-        m.submodules.init = DomainRenamer("init")(ECP5DDRPHYInit("sync2x"))
+        m.submodules.init = init = DomainRenamer("init")(ECP5DDRPHYInit("sync2x"))
 
         # Parameters -------------------------------------------------------------------------------
         cl, cwl = get_cl_cw("DDR3", tck)
@@ -278,8 +278,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                                      i_SCLK=ClockSignal("sync"),
                                      i_ECLK=ClockSignal("sync2x"),
                                      i_RST=ResetSignal("sync2x"),
-                                     i_DDRDEL=self.init.delay,
-                                     i_PAUSE=self.init.pause | self._dly_sel.w_data[i],
+                                     i_DDRDEL=init.delay,
+                                     i_PAUSE=init.pause | self._dly_sel.w_data[i],
 
                                      # Control
                                      # Assert LOADNs to use DDRDEL control
@@ -314,9 +314,9 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             burstdet_d = Signal()
             m.d.sync += burstdet_d.eq(burstdet)
             with m.If(self._burstdet_clr.w_stb):
-                m.d.sync += self._burstdet_seen.status[i].eq(0)
+                m.d.sync += self._burstdet_seen.r_data[i].eq(0)
             with m.If(burstdet & ~burstdet_d):
-                m.d.sync += self._burstdet_seen.status[i].eq(1)
+                m.d.sync += self._burstdet_seen.r_data[i].eq(1)
 
             # DQS and DM ---------------------------------------------------------------------------
             dm_o_data = Signal(8)