Fix wrong T1 signal

[gram.git] / gram / simulation / README.md

diff --git a/gram/simulation/README.md b/gram/simulation/README.md
index fa300c72e07788d3515872491f50b93a3c72b452..4d15f572d2fedeaf871297a798e04cd1c3377c54 100644 (file)
--- a/gram/simulation/README.md
+++ b/gram/simulation/README.md
@@ -4,15 +4,27 @@ This folder contains code used for low level simulation of various aspects of gr
 
 ## Requirements
 
- * Icarius Verilog (preferably a recent version)
+ * Icarus Verilog (built from latest sources)
  * ECP5 instances models from a Lattice Diamond installation (just install Lattice Diamond)
 
 ## Available simulations
 
 ### simcrg
 
+Simulates the CRG used in ECPIX5 gram tests and checks for a few assertions.
+
 ```
 ./runsimcrg.sh
 ```
 
-Produces `simcrg.vcd`.
+Produces `simcrg.fst` (compatbile with Gtkwave).
+
+### simsoc
+
+Simulates a full SoC with a UART Wishbone master and a DDR3 model, and sends the init commands that libgram would send over serial.
+
+```
+./runsimsoc.sh
+```
+
+Produces `simsoc.fst` (compatible with Gtkwave).