Fix CRG, revert to resetful sync domain

[gram.git] / gram / simulation / runsimcrg.sh

diff --git a/gram/simulation/runsimcrg.sh b/gram/simulation/runsimcrg.sh
index 226f409d301b3499f8a0fb2826bba4d47dcba4e9..8491311495b010e063ef6ffef3a3fd6a38b2ebd5 100755 (executable)
--- a/gram/simulation/runsimcrg.sh
+++ b/gram/simulation/runsimcrg.sh
@@ -4,5 +4,5 @@ set -e
 LIB_DIR=/usr/local/diamond/3.11_x64/ispfpga/verilog/data/ecp5u
 
 python simcrg.py generate simcrg.v
-iverilog -o simcrg simcrgtb.v simcrg.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/CLKDIVF.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v
+iverilog -Wall -o simcrg simcrgtb.v simcrg.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/CLKDIVF.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v
 vvp simcrg -vcd