Externalize CRG into its own file

[gram.git] / gram / simulation / runsimsoc.sh

diff --git a/gram/simulation/runsimsoc.sh b/gram/simulation/runsimsoc.sh
index 2fd6c648f0885574d91c0de4dc05af05d4957b40..1722be78b9807a98943a6a394e6f6ec9a0b3b743 100755 (executable)
--- a/gram/simulation/runsimsoc.sh
+++ b/gram/simulation/runsimsoc.sh
@@ -4,8 +4,11 @@ set -e
 LIB_DIR=/usr/local/diamond/3.11_x64/ispfpga/verilog/data/ecp5u
 
 python simsoc.py
-iverilog -Wall -g2012 -s simsoctb -o simsoc simsoctb.v build/top.debug.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
+yosys simsoc.ys
+cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v
+patch DDRDLLA.v < DDRDLLA.patch
+iverilog -Wall -g2012 -s simsoctb -o simsoc simsoctb.v build_simsoc/top.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
        ${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
-       ${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v DDRDLLA.patched.v \
+       ${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v DDRDLLA.v \
        ${LIB_DIR}/CLKDIVF.v
-vvp simsoc -fst-speed
+vvp -n simsoc -fst-speed