Mention contrib/test_failfast in test README

[gram.git] / gram / test / test_common.py

diff --git a/gram/test/test_common.py b/gram/test/test_common.py
index a051f1a8f4638ab62544ded114369fecef2ce4a0..385282c613c50d5d4be385746677b685c4aee1a6 100644 (file)
--- a/gram/test/test_common.py
+++ b/gram/test/test_common.py
@@ -2,42 +2,34 @@
 from nmigen import *
 from nmigen.hdl.ast import Past
 
-from gram.common import DQSPattern, tXXDController
+from gram.common import tXXDController, tFAWController
 from utils import *
 
-class DQSPatternTestCase(FHDLTestCase):
-    def test_async(self):
-        m = Module()
-        m.d.sync += Signal().eq(0) # Workaround for nMigen#417
-        m.submodules.dut = dut = DQSPattern(register=False)
-
-        def process():
-            yield dut.preamble.eq(1) # Preamble=1, Postamble=0
-            yield
-            self.assertEqual((yield dut.o), 0b00010101)
-
-            yield dut.postamble.eq(1) # Preamble=1, Postamble=1
-            yield
-            self.assertEqual((yield dut.o), 0b00010101)
-
-            yield dut.preamble.eq(0) # Preamble=0, Postamble=1
-            yield
-            self.assertEqual((yield dut.o), 0b01010100)
-
-            yield dut.postamble.eq(0) # Preamble=1, Postamble=1
-            yield
-            self.assertEqual((yield dut.o), 0b01010101)
-
-        runSimulation(m, process, "test_dqspattern_async.vcd")
-
 class tXXDControllerTestCase(FHDLTestCase):
     def test_formal(self):
         def generic_test(txxd):
             dut = tXXDController(txxd)
-            self.assertFormal(dut, mode="bmc", depth=4)
+            self.assertFormal(dut, mode="bmc", depth=txxd+1 if txxd is not None else 10)
 
         generic_test(None)
         generic_test(0)
         generic_test(1)
         generic_test(5)
-        generic_test(10)
\ No newline at end of file
+        generic_test(10)
+
+class tFAWControllerTestCase(FHDLTestCase):
+    def test_strobe_3(self):
+        dut = tFAWController(10)
+        def process():
+            yield dut.valid.eq(1)
+            
+            for i in range(3):
+                self.assertTrue((yield dut.ready))
+                yield
+
+            yield dut.valid.eq(0)
+            yield
+
+            self.assertFalse((yield dut.valid))
+
+        runSimulation(dut, process, "test_common.vcd")