Remove unnecessary modules in gram tests

[gram.git] / gram / test / test_core_refresher.py

diff --git a/gram/test/test_core_refresher.py b/gram/test/test_core_refresher.py
index a1f940870da4d929aeee907dec86d824656bc11b..a9685364d2351ac70d5cfa51b6c3dfde987375ff 100644 (file)
--- a/gram/test/test_core_refresher.py
+++ b/gram/test/test_core_refresher.py
@@ -9,8 +9,7 @@ from utils import *
 class RefreshExecuterTestCase(FHDLTestCase):
     def test_executer(self):
         def generic_test(abits, babits, trp, trfc):
-            m = Module()
-            m.submodules.dut = dut = RefreshExecuter(abits=abits, babits=babits, trp=trp, trfc=trfc)
+            dut = RefreshExecuter(abits=abits, babits=babits, trp=trp, trfc=trfc)
 
             def process():
                 yield dut.start.eq(1)
@@ -21,7 +20,7 @@ class RefreshExecuterTestCase(FHDLTestCase):
                     yield
                 self.assertEqual((yield dut.a), 0)
 
-            runSimulation(m, process, "test_refreshexecuter.vcd")
+            runSimulation(dut, process, "test_refreshexecuter.vcd")
 
         generic_test(20, 20, 5, 5)
         generic_test(20, 20, 100, 5)
@@ -41,18 +40,16 @@ class RefreshTimerTestCase(FHDLTestCase):
 
 class RefreshPostponerTestCase(FHDLTestCase):
     def test_init(self):
-        m = Module()
-        m.submodules.dut = dut = RefreshPostponer(1)
+        dut = RefreshPostponer(1)
 
         def process():
             self.assertFalse((yield dut.req_o))
 
-        runSimulation(m, process, "test_refreshpostponer.vcd")
+        runSimulation(dut, process, "test_refreshpostponer.vcd")
 
     def test_delay(self):
         def generic_test(delay):
-            m = Module()
-            m.submodules.dut = dut = RefreshPostponer(delay)
+            dut = RefreshPostponer(delay)
 
             def process():
                 yield dut.req_i.eq(1)
@@ -64,14 +61,13 @@ class RefreshPostponerTestCase(FHDLTestCase):
 
                 self.assertTrue((yield dut.req_o))
 
-            runSimulation(m, process, "test_refreshpostponer.vcd")
+            runSimulation(dut, process, "test_refreshpostponer.vcd")
 
         [generic_test(_) for _ in [1, 5, 10]]
 
     def test_req_not_stuck(self):
         def generic_test(delay):
-            m = Module()
-            m.submodules.dut = dut = RefreshPostponer(delay)
+            dut = RefreshPostponer(delay)
 
             def process():
                 yield dut.req_i.eq(1)
@@ -86,7 +82,7 @@ class RefreshPostponerTestCase(FHDLTestCase):
 
                 self.assertFalse((yield dut.req_o))
 
-            runSimulation(m, process, "test_refreshpostponer.vcd")
+            runSimulation(dut, process, "test_refreshpostponer.vcd")
 
         [generic_test(_) for _ in [1, 5, 10]]
 
@@ -110,12 +106,11 @@ class RefresherTestCase(FHDLTestCase):
 
     def test_init(self):
         def generic_test(postponing):
-            m = Module()
-            m.submodules.dut = dut = Refresher(self.settings, 100e6, postponing)
+            dut = Refresher(self.settings, 100e6, postponing)
 
             def process():
                 self.assertFalse((yield dut.cmd.valid))
 
-            runSimulation(m, process, "test_refresher.vcd")
+            runSimulation(dut, process, "test_refresher.vcd")
 
         [generic_test(_) for _ in [1, 2, 4, 8]]