Mention contrib/test_failfast in test README

[gram.git] / gram / test / test_soc.py

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index 6fe0a236a71d67c0e0395e7454c8b205a1ea404f..fae835cf5ebfedbf4ac54dff15c41fb28fe9809f 100644 (file)
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -135,11 +135,9 @@ class SocTestCase(FHDLTestCase):
             yield
 
     def test_multiple_reads(self):
-        m = Module()
         soc = DDR3SoC(clk_freq=100e6,
             dramcore_addr=0x00000000,
             ddr_addr=0x10000000)
-        m.submodules += soc
 
         def process():
             yield from SocTestCase.init_seq(soc.bus)
@@ -153,14 +151,12 @@ class SocTestCase(FHDLTestCase):
                 yield
                 self.assertEqual(res, 0xACAB2020)
 
-        runSimulation(m, process, "test_soc_multiple_reads.vcd")
+        runSimulation(soc, process, "test_soc_multiple_reads.vcd")
 
     def test_interleaved_read_write(self):
-        m = Module()
         soc = DDR3SoC(clk_freq=100e6,
             dramcore_addr=0x00000000,
             ddr_addr=0x10000000)
-        m.submodules += soc
 
         def process():
             yield from SocTestCase.init_seq(soc.bus)
@@ -180,43 +176,17 @@ class SocTestCase(FHDLTestCase):
             res = yield from wb_read(soc.bus, 0x10000008 >> 2, 0xF, 128)
             self.assertEqual(res, 0xCAFE1000)
 
-        runSimulation(m, process, "test_soc_interleaved_read_write.vcd")
-
-    def test_sequential_reads(self):
-        m = Module()
-        soc = DDR3SoC(clk_freq=100e6,
-            dramcore_addr=0x00000000,
-            ddr_addr=0x10000000)
-        m.submodules += soc
-
-        def process():
-            yield from SocTestCase.init_seq(soc.bus)
-
-            # Should read from same row/col/bank
-            yield from wb_read(soc.bus, 0x10000000 >> 2, 0xF, 128)
-            yield from wb_read(soc.bus, 0x10000004 >> 2, 0xF, 128)
-            yield from wb_read(soc.bus, 0x10000008 >> 2, 0xF, 128)
-            yield from wb_read(soc.bus, 0x1000000C >> 2, 0xF, 128)
-
-            # Should read from a different row
-            yield from wb_read(soc.bus, 0x10000010 >> 2, 0xF, 128)
-            yield from wb_read(soc.bus, 0x10000014 >> 2, 0xF, 128)
-            yield from wb_read(soc.bus, 0x10000018 >> 2, 0xF, 128)
-            yield from wb_read(soc.bus, 0x1000001C >> 2, 0xF, 128)
-
-        runSimulation(m, process, "test_soc_sequential_reads.vcd")
+        runSimulation(soc, process, "test_soc_interleaved_read_write.vcd")
 
     def test_random_memtest(self):
-        m = Module()
         soc = DDR3SoC(clk_freq=100e6,
             dramcore_addr=0x00000000,
             ddr_addr=0x10000000)
-        m.submodules += soc
 
         def process():
             yield from SocTestCase.init_seq(soc.bus)
 
-            n = 100
+            n = 64
 
             memtest_values = []
             for i in range(n):
@@ -230,19 +200,17 @@ class SocTestCase(FHDLTestCase):
             for i in range(n):
                 self.assertEqual(memtest_values[i], (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256)))
 
-        runSimulation(m, process, "test_soc_random_memtest.vcd")
+        runSimulation(soc, process, "test_soc_random_memtest.vcd")
 
     def test_continuous_memtest(self):
-        m = Module()
         soc = DDR3SoC(clk_freq=100e6,
             dramcore_addr=0x00000000,
             ddr_addr=0x10000000)
-        m.submodules += soc
 
         def process():
             yield from SocTestCase.init_seq(soc.bus)
 
-            n = 100
+            n = 128
 
             # Write
             for i in range(n):
@@ -252,4 +220,4 @@ class SocTestCase(FHDLTestCase):
             for i in range(n):
                 self.assertEqual(0xFACE0000 | i, (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256)))
 
-        runSimulation(m, process, "test_soc_continuous_memtest.vcd")
+        runSimulation(soc, process, "test_soc_continuous_memtest.vcd")