class DDR3SoC(SoC, Elaboratable):
def __init__(self, *, clk_freq, dramcore_addr,
ddr_addr):
- self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8,
- features={"cti", "bte"})
self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})
self.bus = wishbone.Interface(addr_width=30, data_width=32, granularity=32)
- self._arbiter.add(self.bus)
tck = 2/(2*2*100e6)
nphases = 2
def elaborate(self, platform):
m = Module()
- m.submodules.arbiter = self._arbiter
-
m.submodules.decoder = self._decoder
m.submodules.ddrphy = self.ddrphy
m.submodules.dramcore = self.dramcore
m.submodules.drambone = self.drambone
m.d.comb += [
- self._arbiter.bus.connect(self._decoder.bus),
+ self.bus.connect(self._decoder.bus),
]
return m
yield
def test_multiple_reads(self):
- m = Module()
soc = DDR3SoC(clk_freq=100e6,
dramcore_addr=0x00000000,
ddr_addr=0x10000000)
- m.submodules += soc
def process():
yield from SocTestCase.init_seq(soc.bus)
yield
self.assertEqual(res, 0xACAB2020)
- runSimulation(m, process, "test_soc_multiple_reads.vcd")
+ runSimulation(soc, process, "test_soc_multiple_reads.vcd")
def test_interleaved_read_write(self):
- m = Module()
soc = DDR3SoC(clk_freq=100e6,
dramcore_addr=0x00000000,
ddr_addr=0x10000000)
- m.submodules += soc
def process():
yield from SocTestCase.init_seq(soc.bus)
res = yield from wb_read(soc.bus, 0x10000008 >> 2, 0xF, 128)
self.assertEqual(res, 0xCAFE1000)
- runSimulation(m, process, "test_soc_interleaved_read_write.vcd")
-
- def test_sequential_reads(self):
- m = Module()
- soc = DDR3SoC(clk_freq=100e6,
- dramcore_addr=0x00000000,
- ddr_addr=0x10000000)
- m.submodules += soc
-
- def process():
- yield from SocTestCase.init_seq(soc.bus)
-
- # Should read from same row/col/bank
- yield from wb_read(soc.bus, 0x10000000 >> 2, 0xF, 128)
- yield from wb_read(soc.bus, 0x10000004 >> 2, 0xF, 128)
- yield from wb_read(soc.bus, 0x10000008 >> 2, 0xF, 128)
- yield from wb_read(soc.bus, 0x1000000C >> 2, 0xF, 128)
-
- # Should read from a different row
- yield from wb_read(soc.bus, 0x10000010 >> 2, 0xF, 128)
- yield from wb_read(soc.bus, 0x10000014 >> 2, 0xF, 128)
- yield from wb_read(soc.bus, 0x10000018 >> 2, 0xF, 128)
- yield from wb_read(soc.bus, 0x1000001C >> 2, 0xF, 128)
-
- runSimulation(m, process, "test_soc_sequential_reads.vcd")
+ runSimulation(soc, process, "test_soc_interleaved_read_write.vcd")
def test_random_memtest(self):
- m = Module()
soc = DDR3SoC(clk_freq=100e6,
dramcore_addr=0x00000000,
ddr_addr=0x10000000)
- m.submodules += soc
def process():
yield from SocTestCase.init_seq(soc.bus)
- n = 100
+ n = 64
memtest_values = []
for i in range(n):
for i in range(n):
self.assertEqual(memtest_values[i], (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256)))
- runSimulation(m, process, "test_soc_random_memtest.vcd")
+ runSimulation(soc, process, "test_soc_random_memtest.vcd")
def test_continuous_memtest(self):
- m = Module()
soc = DDR3SoC(clk_freq=100e6,
dramcore_addr=0x00000000,
ddr_addr=0x10000000)
- m.submodules += soc
def process():
yield from SocTestCase.init_seq(soc.bus)
- n = 100
+ n = 128
# Write
for i in range(n):
for i in range(n):
self.assertEqual(0xFACE0000 | i, (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256)))
- runSimulation(m, process, "test_soc_continuous_memtest.vcd")
+ runSimulation(soc, process, "test_soc_continuous_memtest.vcd")