Add temporary code for SoC tests with FakePHY

[gram.git] / gram / test / utils.py

diff --git a/gram/test/utils.py b/gram/test/utils.py
index 38b8010dbaf5fbba3b273df18ef7d092d6ea818e..67124296d3ca276ab4022a7782a2702dfe14b285 100644 (file)
--- a/gram/test/utils.py
+++ b/gram/test/utils.py
@@ -15,7 +15,7 @@ from nmigen.back import rtlil
 from nmigen._toolchain import require_tool
 
 
-__all__ = ["FHDLTestCase", "runSimulation"]
+__all__ = ["FHDLTestCase", "runSimulation", "wb_read", "wb_write", "PulseCounter"]
 
 def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-6):
     sim = Simulator(module)
@@ -92,7 +92,6 @@ class FHDLTestCase(unittest.TestCase):
         """).format(
             mode=mode,
             depth=depth,
-            script=script,
             rtlil=rtlil.convert(Fragment.get(spec, platform="formal"))
         )
         with subprocess.Popen([require_tool("sby"), "-f", "-d", spec_name],
@@ -103,3 +102,54 @@ class FHDLTestCase(unittest.TestCase):
             stdout, stderr = proc.communicate(config)
             if proc.returncode != 0:
                 self.fail("Formal verification failed:\n" + stdout)
+
+def wb_read(bus, addr, sel, timeout=32):
+    yield bus.cyc.eq(1)
+    yield bus.stb.eq(1)
+    yield bus.adr.eq(addr)
+    yield bus.sel.eq(sel)
+    yield
+    cycles = 0
+    while not (yield bus.ack):
+        yield
+        if cycles >= timeout:
+            raise RuntimeError("Wishbone transaction timed out")
+        cycles += 1
+    data = (yield bus.dat_r)
+    yield bus.cyc.eq(0)
+    yield bus.stb.eq(0)
+    return data
+
+def wb_write(bus, addr, data, sel, timeout=32):
+    yield bus.cyc.eq(1)
+    yield bus.stb.eq(1)
+    yield bus.adr.eq(addr)
+    yield bus.we.eq(1)
+    yield bus.sel.eq(sel)
+    yield bus.dat_w.eq(data)
+    yield
+    cycles = 0
+    while not (yield bus.ack):
+        yield
+        if cycles >= timeout:
+            raise RuntimeError("Wishbone transaction timed out")
+        cycles += 1
+    yield bus.cyc.eq(0)
+    yield bus.stb.eq(0)
+    yield bus.we.eq(0)
+
+class PulseCounter(Elaboratable):
+    def __init__(self, max=16):
+        self.i = Signal()
+        self.rst = Signal()
+        self.cnt = Signal(range(max))
+
+    def elaborate(self, platform):
+        m = Module()
+
+        with m.If(self.rst):
+            m.d.sync += self.cnt.eq(0)
+        with m.Elif(self.i):
+            m.d.sync += self.cnt.eq(self.cnt+1)
+
+        return m