**MVL, setvl instruction & VL CSR work as per RV Vector spec.**
-## VLD and VST are supported
+**VLD and VST are supported**
RVP implementations may choose to load/store to/from Integer register file
(rather than from a dedicated Vector register file).
harmless but redundant when RVP code is run on a machine with a dedicated
vector reg file).
-## VLDX, VSTX, VLDS, VSTS are not supported in hardware
+**VLDX, VSTX, VLDS, VSTS are not supported in hardware**
To keep RVP implementations simple, these instructions will trap, and
may be implemented as software emulation
-## Default register "banks" and types
+**Default register "banks" and types**
In the absence of an explicit VCFG setup, the vector registers (when
shared with Integer register file) are to default into two “banks”
as follows:
-* v0-v15: vectors with INT8 elements, split into 8 x signed (v0-v7)
- & 8 x unsigned (v8-v15)
-* v16-v29: vectors with INT16 elements, split into 8 x signed (v16-v23)
- & 6 x unsigned (v24-v29)
+* v0-v15: vectors with INT8 elements, split into signed (v0-v7)
+ & unsigned (v8-v15)
+* v16-v29: vectors with INT16 elements, split into signed (v16-v23)
+ & unsigned (v24-v29)
Having the above default vector type configuration harmonises most of
the Andes SIMD instruction set (which explicitly encodes INT8 vs INT16
* v0 is mapped to r1 (hardwired to zero), and v1 is used for predicate
masks. However, both can be considered INT8 vectors.
-## Default MVL
+**Default MVL**
The default RVV MVL value (in absence of explicit VCFG setup) is to
be MVL = 2 on RV32I machines and MVL = 4 on RV64I machines. However,
where full Andes SIMD compliance is required (without RVV forward
compatibility), LW/LD and SW/SD are to be used instead of VLD and VST.
-## Alternative register "banks" and alternative MVL
+**Alternative register "banks" and alternative MVL**
A programmer can configure VCFG with any mix of these alternative
configurations: