signal rst : std_ulogic;
signal i_out : Fetch1ToIcacheType;
- signal i_in : IcacheToFetch2Type;
+ signal i_in : IcacheToDecode1Type;
signal m_out : MmuToIcacheType;
i_in => i_out,
i_out => i_in,
m_in => m_out,
- flush_in => '0',
+ stall_in => '0',
+ flush_in => '0',
inval_in => '0',
wishbone_out => wb_bram_in,
wishbone_in => wb_bram_out
begin
i_out.req <= '0';
i_out.nia <= (others => '0');
- i_out.stop_mark <= '0';
+ i_out.stop_mark <= '0';
m_out.tlbld <= '0';
m_out.tlbie <= '0';
assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000001"
- report "insn @" & to_hstring(i_out.nia) &
- "=" & to_hstring(i_in.insn) &
- " expected 00000001"
- severity failure;
+ report "insn @" & to_hstring(i_out.nia) &
+ "=" & to_hstring(i_in.insn) &
+ " expected 00000001"
+ severity failure;
i_out.req <= '0';
wait until rising_edge(clk);
assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000002"
- report "insn @" & to_hstring(i_out.nia) &
- "=" & to_hstring(i_in.insn) &
- " expected 00000002"
- severity failure;
+ report "insn @" & to_hstring(i_out.nia) &
+ "=" & to_hstring(i_in.insn) &
+ " expected 00000002"
+ severity failure;
wait until rising_edge(clk);
-- another miss
assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000010"
- report "insn @" & to_hstring(i_out.nia) &
- "=" & to_hstring(i_in.insn) &
- " expected 00000010"
- severity failure;
+ report "insn @" & to_hstring(i_out.nia) &
+ "=" & to_hstring(i_in.insn) &
+ " expected 00000010"
+ severity failure;
-- test something that aliases
i_out.req <= '1';
assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000040"
- report "insn @" & to_hstring(i_out.nia) &
- "=" & to_hstring(i_in.insn) &
- " expected 00000040"
- severity failure;
+ report "insn @" & to_hstring(i_out.nia) &
+ "=" & to_hstring(i_in.insn) &
+ " expected 00000040"
+ severity failure;
i_out.req <= '0';