Commit missing ChangeLog entry for Cortex-M33 support

[binutils-gdb.git] / include / ChangeLog

diff --git a/include/ChangeLog b/include/ChangeLog
index 7b44b04bb9662dc98f9283349e8b15b6214e3f2a..0a3b51e3956e8618a43d6742e8a351bf2fce3e01 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,40 @@
+2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
+       (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
+       (ARM_ARCH_V8M_MAIN_DSP): Likewise.
+
+2016-11-03  Graham Markall  <graham.markall@embecosm.com>
+
+       * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
+
+2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
+       fields.
+       (struct arc_long_opcode): Delete.
+       (struct arc_operand): Change types for insert and extract
+       handlers.
+
+2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * opcode/arc.h: Make macros 64-bit safe.
+
+2016-11-03  Graham Markall  <graham.markall@embecosm.com>
+
+       * opcode/arc.h (arc_opcode_len): Declare.
+       (ARC_SHORT): Delete.
+
+2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
+           Andrew Waterman <andrew@sifive.com>
+
+       Add support for RISC-V architecture.
+       * dis-asm.h: Add prototypes for print_insn_riscv and
+       print_riscv_disassembler_options.
+       * elf/riscv.h: New file.
+       * opcode/riscv-opc.h: New file.
+       * opcode/riscv.h: New file.
+
 2016-10-17  Nick Clifton  <nickc@redhat.com>
 
        * elf/common.h (DT_SYMTAB_SHNDX): Define.