+2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
+ (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
+ (ARM_ARCH_V8M_MAIN_DSP): Likewise.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
+
+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
+ fields.
+ (struct arc_long_opcode): Delete.
+ (struct arc_operand): Change types for insert and extract
+ handlers.
+
+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h: Make macros 64-bit safe.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * opcode/arc.h (arc_opcode_len): Declare.
+ (ARC_SHORT): Delete.
+
+2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ Add support for RISC-V architecture.
+ * dis-asm.h: Add prototypes for print_insn_riscv and
+ print_riscv_disassembler_options.
+ * elf/riscv.h: New file.
+ * opcode/riscv-opc.h: New file.
+ * opcode/riscv.h: New file.
+
+2016-10-17 Nick Clifton <nickc@redhat.com>
+
+ * elf/common.h (DT_SYMTAB_SHNDX): Define.
+ (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
+ (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
+ (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
+ (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
+ (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
+ (ELFOSABI_OPENVOS): Define.
+ (GRP_MASKOS, GRP_MASKPROC): Define.
+
2016-10-14 Pedro Alves <palves@redhat.com>
* ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,