+2018-11-27 Jim Wilson <jimw@sifive.com>
+
+ * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New.
+ (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New.
+
+2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M.
+ (ARM_ARCH_V6M_ONLY): Remove.
+ (ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M,
+ ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP,
+ ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8,
+ ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM,
+ ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M,
+ ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP,
+ ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN,
+ ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M,
+ ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A,
+ ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A,
+ ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK,
+ ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG,
+ FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD,
+ FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3,
+ FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
+ FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8,
+ FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD,
+ FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2,
+ ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4,
+ ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5,
+ ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE,
+ ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ,
+ ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2,
+ ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R,
+ ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM,
+ ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A,
+ ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A,
+ ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN,
+ ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE,
+ ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R,
+ ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16,
+ FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16,
+ FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8,
+ FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA,
+ FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2,
+ FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16,
+ FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1,
+ FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4,
+ FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16,
+ FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8,
+ FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8,
+ FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
+ FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2,
+ ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4,
+ ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5,
+ ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE,
+ ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ,
+ ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2,
+ ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE,
+ ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A,
+ ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A,
+ ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN,
+ ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
+ (aarch64_insn_class): Add ldstgv_indexed.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
+ and AARCH64_OPND_ADDR_SIMM13.
+ (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (aarch64_opnd): Add
+ AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
+
2018-11-07 Roman Bolshakov <r.bolshakov@yadro.com>
Saagar Jha <saagar@saagarjha.com>
projects / binutils-gdb.git / blobdiff