-2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+2020-02-20 Nelson Chu <nelson.chu@sifive.com>
- * elf/arm.h (Tag_MVE_arch): Define new enum value.
- * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
+ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
+ record riscv_csr_class.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
+ Matthew Malcomson <matthew.malcomson@arm.com>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
- operand.
+ * opcode/arm.h (ARM_EXT2_CDE): New extension macro.
+ (ARM_EXT2_CDE0): New extension macro.
+ (ARM_EXT2_CDE1): New extension macro.
+ (ARM_EXT2_CDE2): New extension macro.
+ (ARM_EXT2_CDE3): New extension macro.
+ (ARM_EXT2_CDE4): New extension macro.
+ (ARM_EXT2_CDE5): New extension macro.
+ (ARM_EXT2_CDE6): New extension macro.
+ (ARM_EXT2_CDE7): New extension macro.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
- iclass.
+ PR 25469
+ * coff/internal.h (R_IMM16BE): Define.
+ * elf/z80.h (EF_Z80_MACH_Z80N): Define.
+ (R_Z80_16_BE): New reloc.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-02-04 Alan Modra <amodra@gmail.com>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
+ * opcode/d30v.h (struct pd_reg): Make value field unsigned.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-01-16 Jon Turney <jon.turney@dronecode.org.uk>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
- iclass.
+ * coff/internal.h (PE_IMAGE_DEBUG_TYPE_VC_FEATURE)
+ (PE_IMAGE_DEBUG_TYPE_POGO, PE_IMAGE_DEBUG_TYPE_ILTCG)
+ (PE_IMAGE_DEBUG_TYPE_MPX, PE_IMAGE_DEBUG_TYPE_REPRO): Add.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-01-18 Nick Clifton <nickc@redhat.com>
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
- operand.
- (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
+ Binutils 2.34 branch created.
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+2020-01-17 Nick Clifton <nickc@redhat.com>
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
+ * Import from gcc mainline:
+ 2019-06-10 Martin Liska <mliska@suse.cz>
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * ansidecl.h (ATTRIBUTE_WARN_UNUSED_RESULT): New macro.
+ * libiberty.h (xmalloc): Use it.
+ (xrealloc): Likewise.
+ (xcalloc): Likewise.
+ (xstrdup): Likewise.
+ (xstrndup): Likewise.
+ (xmemdup): Likewise.
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
+ 2019-06-10 Martin Liska <mliska@suse.cz>
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * ansidecl.h:
+ (ATTRIBUTE_RESULT_SIZE_1): Define new macro.
+ (ATTRIBUTE_RESULT_SIZE_2): Likewise.
+ (ATTRIBUTE_RESULT_SIZE_1_2): Likewise.
+ * libiberty.h (xmalloc): Add RESULT_SIZE attribute.
+ (xrealloc): Likewise.
+ (xcalloc): Likewise.
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.
+ 2019-11-16 Tim Ruehsen <tim.ruehsen@gmx.de>
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * demangle.h (struct demangle_component): Add member
+ d_counting.
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
+ 2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs>
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * demangle.h (rust_demangle_callback): Add.
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
+ 2019-07-18 Eduard-Mihai Burtescu <eddyb@lyken.rs>
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * demangle.h (rust_is_mangled): Move to libiberty/rust-demangle.h.
+ (rust_demangle_sym): Move to libiberty/rust-demangle.h.
- * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
+2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ PR 25376
+ * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
+ (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
+ (ARM_ANY): Redefine to not include any MVE bits.
+ (ARM_FEATURE_ALL): Removed.
- * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
+2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
-2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * opcode/msp430.h (enum msp430_expp_e): New.
+ (struct msp430_operand_s): Add expp member to struct.
- * opcode/aarch64.h (AARCH64_FEATURE_SVE2
- AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
- AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
- feature macros.
+2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
-2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
- Faraz Shahbazker <fshahbazker@wavecomp.com>
+ * elf/arc-cpu.def: Update ARC cpu list.
- * opcode/mips.h (ASE_EVA_R6): New macro.
- (M_LLWPE_AB, M_SCWPE_AB): New enum values.
+2020-01-13 Alan Modra <amodra@gmail.com>
-2019-05-01 Sudakshina Das <sudi.das@arm.com>
+ * opcode/tic4x.h (EXTR): Delete.
+ (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
+ extension using shifts. Do trim INSERTU value to specified bitfield.
- * opcode/aarch64.h (AARCH64_FEATURE_TME): New.
- (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
+2020-01-10 Alan Modra <amodra@gmail.com>
-2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
- Faraz Shahbazker <fshahbazker@wavecomp.com>
+ * opcode/spu.h: Formatting.
+ (UNSIGNED_EXTRACT): Use 1u.
+ (SIGNED_EXTRACT): Don't sign extend with shifts.
+ (DECODE_INSN_I9a, DECODE_INSN_I9b): Avoid left shift of signed value.
+ Keep result signed.
+ (DECODE_INSN_U9a, DECODE_INSN_U9b): Delete.
- * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
- (M_SCWP_AB, M_SCDP_AB): Likewise.
+2020-01-07 Shahab Vahedi <shahab@synopsys.com>
-2019-04-25 Maciej W. Rozycki <macro@linux-mips.org>
+ * opcode/arc.h (insn_class_t): Add 'LLOCK' and 'SCOND'.
- * opcode/mips.h: Update comment for MIPS32 CODE20 operand.
+2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
-2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ * coff/internal.h: Add defintions of Z80 reloc names.
- * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
+2020-01-02 Christian Biesinger <cbiesinger@google.com>
-2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ * opcode/s12z.h: Undef REG_Y.
- * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
-
-2019-04-15 Sudakshina Das <sudi.das@arm.com>
-
- * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
-
-2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
-
- * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
- (MAX_TAG_CPU_ARCH): Set value to above macro.
- * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
- (ARM_AEXT_V8_1M_MAIN): Likewise.
- (ARM_AEXT2_V8_1M_MAIN): Likewise.
- (ARM_ARCH_V8_1M_MAIN): Likewise.
-
-2019-04-11 Sudakshina Das <sudi.das@arm.com>
-
- * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
-
-2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
-
- * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
-
-2019-04-07 Alan Modra <amodra@gmail.com>
-
- Merge from gcc.
- 2019-04-03 Vineet Gupta <vgupta@synopsys.com>
- PR89877
- * longlong.h [__arc__] (add_ssaaaa): Add cc clobber.
- (sub_ddmmss): Likewise.
-
-2019-04-06 H.J. Lu <hongjiu.lu@intel.com>
-
- * bfdlink.h (bfd_link_info): Remove x86-specific linker options.
-
-2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * opcode/arm.h (FPU_NEON_ARMV8_1): New.
- (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.
- (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.
- (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.
- (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.
- (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.
- (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.
- (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.
-
-2019-03-28 Alan Modra <amodra@gmail.com>
-
- PR 24390
- * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
-
-2019-03-25 Tamar Christina <tamar.christina@arm.com>
-
- * dis-asm.h (struct disassemble_info): Add stop_offset.
-
-2019-03-13 Sudakshina Das <sudi.das@arm.com>
-
- * elf/aarch64.h (DT_AARCH64_PAC_PLT): New.
-
-2019-03-13 Sudakshina Das <sudi.das@arm.com>
- Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
-
-2019-03-13 Sudakshina Das <sudi.das@arm.com>
-
- * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
- (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
- (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.
-
-2019-02-20 Alan Hayward <alan.hayward@arm.com>
-
- * elf/common.h (NT_ARM_PAC_MASK): Add define.
-
-2019-02-15 Saagar Jha <saagar@saagarjha.com>
-
- * mach-o/loader.h: Use new OS names in comments.
-
-2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be>
-
- * splay-tree.h (splay_tree_delete_key_fn): Update comment.
- (splay_tree_delete_value_fn): Likewise.
-
-2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * opcode/s390.h (enum s390_opcode_cpu_val): Add
- S390_OPCODE_ARCH13.
-
-2019-01-25 Sudakshina Das <sudi.das@arm.com>
- Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
-
- * opcode/aarch64.h (enum aarch64_opnd): Remove
- AARCH64_OPND_ADDR_SIMPLE_2.
- (enum aarch64_insn_class): Remove ldstgv_indexed.
-
-2019-01-22 Tom Tromey <tom@tromey.com>
-
- * coff/ecoff.h: Include coff/sym.h.
-
-2018-06-24 Nick Clifton <nickc@redhat.com>
-
- 2.32 branch created.
-
-2019-01-16 Kito Cheng <kito@andestech.com>
-
- * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
- (Tag_RISCV_arch): Likewise.
- (Tag_RISCV_priv_spec): Likewise.
- (Tag_RISCV_priv_spec_minor): Likewise.
- (Tag_RISCV_priv_spec_revision): Likewise.
- (Tag_RISCV_unaligned_access): Likewise.
- (Tag_RISCV_stack_align): Likewise.
-
-2019-01-14 Pavel I. Kryukov <kryukov@frtk.ru>
-
- * dis-asm.h: include <string.h>
-
-2019-01-10 Nick Clifton <nickc@redhat.com>
-
- * Merge from GCC:
- 2018-12-22 Jason Merrill <jason@redhat.com>
-
- * demangle.h: Remove support for ancient GNU (pre-3.0), Lucid,
- ARM, HP, and EDG demangling styles.
-
-2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
-
- Merge from GCC:
- PR other/16615
-
- * libiberty.h: Mechanically replace "can not" with "cannot".
- * plugin-api.h: Likewise.
-
-2018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp>
-
- * elf/rx.h (EF_RX_CPU_MASK): Update new bits.
- (E_FLAG_RX_V3): New RXv3 type.
- * opcode/rx.h (RX_Size): Add double size.
- (RX_Operand_Type): Add double FPU registers.
- (RX_Opcode_ID): Add new instuctions.
-
-2019-01-01 Alan Modra <amodra@gmail.com>
+2020-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
-For older changes see ChangeLog-2018
+For older changes see ChangeLog-2019
\f
-Copyright (C) 2019 Free Software Foundation, Inc.
+Copyright (C) 2020 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / binutils-gdb.git / blobdiff