+2011-11-01 DJ Delorie <dj@redhat.com>
+
+ * rl78.h: New file.
+
+2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Fix a typo in description.
+
+2011-09-21 David S. Miller <davem@davemloft.net>
+
+ * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
+ (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
+ F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
+ F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
+
+2011-08-09 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
+ (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
+ (INSN_ASE_MASK): Add the MCU bit.
+ (INSN_MCU): New macro.
+ (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
+ (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
+
+2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
+ (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
+ (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
+ (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
+ (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
+ (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
+ (INSN2_READ_GPR_MMN): Likewise.
+ (INSN2_READ_FPR_D): Change the bit used.
+ (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
+ (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
+ (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
+ (INSN2_COND_BRANCH): Likewise.
+ (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
+ (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
+ (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
+ (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
+ (INSN2_MOD_GPR_MN): Likewise.
+
+2011-08-05 David S. Miller <davem@davemloft.net>
+
+ * sparc.h: Document new format codes '4', '5', and '('.
+ (OPF_LOW4, RS3): New macros.
+
+2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
+ order of flags documented.
+
+2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Clarify the description of microMIPS instruction
+ manipulation macros.
+ (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
+
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
+ (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
+ (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
+ (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
+ (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
+ (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
+ (OP_MASK_RS3, OP_SH_RS3): Likewise.
+ (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
+ (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
+ (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
+ (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
+ (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
+ (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
+ (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
+ (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
+ (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
+ (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
+ (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
+ (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
+ (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
+ (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
+ (INSN_WRITE_GPR_S): New macro.
+ (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
+ (INSN2_READ_FPR_D): Likewise.
+ (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
+ (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
+ (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
+ (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
+ (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
+ (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
+ (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
+ (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
+ (CPU_MICROMIPS): New macro.
+ (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
+ (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
+ (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
+ (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
+ (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
+ (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
+ (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
+ (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
+ (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
+ (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
+ (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
+ (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
+ (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
+ (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
+ (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
+ (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
+ (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
+ (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
+ (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
+ (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
+ (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
+ (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
+ (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
+ (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
+ (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
+ (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
+ (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
+ (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
+ (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
+ (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
+ (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
+ (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
+ (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
+ (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
+ (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
+ (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
+ (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
+ (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
+ (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
+ (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
+ (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
+ (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
+ (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
+ (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
+ (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
+ (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
+ (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
+ (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
+ (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
+ (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
+ (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
+ (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
+ (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
+ (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
+ (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
+ (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
+ (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
+ (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
+ (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
+ (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
+ (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
+ (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
+ (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
+ (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
+ (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
+ (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
+ (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
+ (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
+ (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
+ (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
+ (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
+ (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
+ (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
+ (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
+ (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
+ (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
+ (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
+ (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
+ (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
+ (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
+ (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
+ (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
+ (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
+ (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
+ (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
+ (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
+ (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
+ (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
+ (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+ (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
+ (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+ (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+ (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+ (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+ (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+ (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
+ (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+ (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
+ (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
+ (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
+ (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
+ (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
+ (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
+ (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
+ (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
+ (micromips_opcodes): New declaration.
+ (bfd_micromips_num_opcodes): Likewise.
+
+2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (INSN_TRAP): Rename to...
+ (INSN_NO_DELAY_SLOT): ... this.
+ (INSN_SYNC): Remove macro.
+
+2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
+ a duplicate of AVR_ISA_SPM.
+
+2011-07-01 Nick Clifton <nickc@redhat.com>
+
+ * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
+
+2011-06-18 Robin Getz <robin.getz@analog.com>
+
+ * bfin.h (is_macmod_signed): New func
+
+2011-06-18 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin.h (is_macmod_pmove): Add missing space before func args.
+ (is_macmod_hmove): Likewise.
+
+2011-06-13 Walter Lee <walt@tilera.com>
+
+ * tilegx.h: New file.
+ * tilepro.h: New file.
+
+2011-05-31 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (ARM_ARCH_V7R_IDIV): Define.
+
+2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390.h: Replace S390_OPERAND_REG_EVEN with
+ S390_OPERAND_REG_PAIR.
+
+2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390.h: Add S390_OPCODE_REG_EVEN flag.
+
+2011-04-18 Julian Brown <julian@codesourcery.com>
+
+ * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
+
+2011-04-11 Dan McDonald <dan@wellkeeper.com>
+
+ PR gas/12296
+ * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
+
+2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
+ New instruction set flags.
+ (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
+
+2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (M_PREF_AB): New enum value.
+
+2011-02-12 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
+ M_IU): Define.
+ (is_macmod_pmove, is_macmod_hmove): New functions.
+
+2011-02-11 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
+
+2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
+
+ * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
+ * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
+
+2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ PR gas/11395
+ * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
+ "bb" entries.
+
+2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ PR gas/11395
+ * hppa.h: Clear "d" bit in "add" and "sub" patterns.
+
+2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Update commentary after last commit.
+
+2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
+
+ * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
+ (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
+ (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
+
+2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
+
+2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Fix previous commit.
+
+2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
+
+ * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
+ (INSN_LOONGSON_3A): Clear bit 31.
+
+2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ PR gas/12198
+ * arm.h (ARM_AEXT_V6M_ONLY): New define.
+ (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
+ (ARM_ARCH_V6M_ONLY): New define.
+
+2010-11-11 Mingming Sun <mingm.sun@gmail.com>
+
+ * mips.h (INSN_LOONGSON_3A): Defined.
+ (CPU_LOONGSON_3A): Defined.
+ (OPCODE_IS_MEMBER): Add LOONGSON_3A.
+
+2010-10-09 Matt Rice <ratmice@gmail.com>
+
+ * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
+ (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm.h (ARM_EXT_VIRT): New define.
+ (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
+ (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
+ Extensions.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm.h (ARM_AEXT_ADIV): New define.
+ (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm.h (ARM_EXT_OS): New define.
+ (ARM_AEXT_V6SM): Likewise.
+ (ARM_ARCH_V6SM): Likewise.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * arm.h (ARM_EXT_MP): Add.
+ (ARM_ARCH_V7A_MP): Likewise.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin.h: Declare pseudoChr structs/defines.
+
+2010-09-21 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin.h: Strip trailing whitespace.
+
+2010-07-29 DJ Delorie <dj@redhat.com>
+
+ * rx.h (RX_Operand_Type): Add TwoReg.
+ (RX_Opcode_ID): Remove ediv and ediv2.
+
+2010-07-27 DJ Delorie <dj@redhat.com>
+
+ * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
+
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
+ PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
+ PROCESSOR_V850E2_ALL.
+ Remove PROCESSOR_V850EA support.
+ (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
+ V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
+ V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
+ V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
+ V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
+ V850_OPERAND_PERCENT.
+ Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
+ V850_NOT_R0.
+ Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
+ and V850E_PUSH_POP
+
+2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
+ (MIPS16_INSN_BRANCH): Rename to...
+ (MIPS16_INSN_COND_BRANCH): ... this.
+
+2010-07-03 Alan Modra <amodra@gmail.com>
+
+ * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
+ Renumber other PPC_OPCODE defines.
+
+2010-07-03 Alan Modra <amodra@gmail.com>
+
+ * ppc.h (PPC_OPCODE_COMMON): Expand comment.
+
+2010-06-29 Alan Modra <amodra@gmail.com>
+
+ * maxq.h: Delete file.
+
+2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+
+ * ppc.h (PPC_OPCODE_E500): Define.
+
+2010-05-26 Catherine Moore <clm@codesourcery.com>
+
+ * opcode/mips.h (INSN_MIPS16): Remove.
+
+2010-04-21 Joseph Myers <joseph@codesourcery.com>
+
+ * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
+
+2010-04-15 Nick Clifton <nickc@redhat.com>
+
+ * alpha.h: Update copyright notice to use GPLv3.
+ * arc.h: Likewise.
+ * arm.h: Likewise.
+ * avr.h: Likewise.
+ * bfin.h: Likewise.
+ * cgen.h: Likewise.
+ * convex.h: Likewise.
+ * cr16.h: Likewise.
+ * cris.h: Likewise.
+ * crx.h: Likewise.
+ * d10v.h: Likewise.
+ * d30v.h: Likewise.
+ * dlx.h: Likewise.
+ * h8300.h: Likewise.
+ * hppa.h: Likewise.
+ * i370.h: Likewise.
+ * i386.h: Likewise.
+ * i860.h: Likewise.
+ * i960.h: Likewise.
+ * ia64.h: Likewise.
+ * m68hc11.h: Likewise.
+ * m68k.h: Likewise.
+ * m88k.h: Likewise.
+ * maxq.h: Likewise.
+ * mips.h: Likewise.
+ * mmix.h: Likewise.
+ * mn10200.h: Likewise.
+ * mn10300.h: Likewise.
+ * msp430.h: Likewise.
+ * np1.h: Likewise.
+ * ns32k.h: Likewise.
+ * or32.h: Likewise.
+ * pdp11.h: Likewise.
+ * pj.h: Likewise.
+ * pn.h: Likewise.
+ * ppc.h: Likewise.
+ * pyr.h: Likewise.
+ * rx.h: Likewise.
+ * s390.h: Likewise.
+ * score-datadep.h: Likewise.
+ * score-inst.h: Likewise.
+ * sparc.h: Likewise.
+ * spu-insns.h: Likewise.
+ * spu.h: Likewise.
+ * tic30.h: Likewise.
+ * tic4x.h: Likewise.
+ * tic54x.h: Likewise.
+ * tic80.h: Likewise.
+ * v850.h: Likewise.
+ * vax.h: Likewise.
+
+2010-03-25 Joseph Myers <joseph@codesourcery.com>
+
+ * tic6x-control-registers.h, tic6x-insn-formats.h,
+ tic6x-opcode-table.h, tic6x.h: New.
+
+2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
+
+ * mips.h: (LOONGSON2F_NOP_INSN): New macro.
+
+2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+
+ * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
+
+2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * ia64.h (ia64_find_opcode): Remove argument name.
+ (ia64_find_next_opcode): Likewise.
+ (ia64_dis_opcode): Likewise.
+ (ia64_free_opcode): Likewise.
+ (ia64_find_dependency): Likewise.
+
+2009-11-22 Doug Evans <dje@sebabeach.org>
+
+ * cgen.h: Include bfd_stdint.h.
+ (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
+
+2009-11-18 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
+
+2009-11-17 Paul Brook <paul@codesourcery.com>
+ Daniel Jacobowitz <dan@codesourcery.com>
+
+ * arm.h (ARM_EXT_V6_DSP): Define.
+ (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
+ (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
+
+2009-11-04 DJ Delorie <dj@redhat.com>
+
+ * rx.h (rx_decode_opcode) (mvtipl): Add.
+ (mvtcp, mvfcp, opecp): Remove.
+
+2009-11-02 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
+ FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
+ (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
+ FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
+ FPU_ARCH_NEON_VFP_V4): Define.
+
+2009-10-23 Doug Evans <dje@sebabeach.org>
+
+ * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
+ * cgen.h: Update. Improve multi-inclusion macro name.
+
+2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPCODE_476): Define.
+
+2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
+
+2009-09-29 DJ Delorie <dj@redhat.com>
+
+ * rx.h: New file.
+
+2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (ppc_cpu_t): Typedef to uint64_t.
+
+2009-09-21 Ben Elliston <bje@au.ibm.com>
+
+ * ppc.h (PPC_OPCODE_PPCA2): New.
+
+2009-09-05 Martin Thuresson <martin@mtme.org>
+
+ * ia64.h (struct ia64_operand): Renamed member class to op_class.
+
+2009-08-29 Martin Thuresson <martin@mtme.org>
+
+ * tic30.h (template): Rename type template to
+ insn_template. Updated code to use new name.
+ * tic54x.h (template): Rename type template to
+ insn_template.
+
+2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
+
+ * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
+
+2009-06-11 Anthony Green <green@moxielogic.com>
+
+ * moxie.h (MOXIE_F3_PCREL): Define.
+ (moxie_form3_opc_info): Grow.
+
+2009-06-06 Anthony Green <green@moxielogic.com>
+
+ * moxie.h (MOXIE_F1_M): Define.
+
+2009-04-15 Anthony Green <green@moxielogic.com>
+
+ * moxie.h: Created.
+
+2009-04-06 DJ Delorie <dj@redhat.com>
+
+ * h8300.h: Add relaxation attributes to MOVA opcodes.
+
+2009-03-10 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc.h (ppc_parse_cpu): Declare.
+
+2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
+
+ * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
+ and _IMM11 for mbitclr and mbitset.
+ * score-datadep.h: Update dependency information.
+
+2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPCODE_POWER7): New.
+
+2009-02-06 Doug Evans <dje@google.com>
+
+ * i386.h: Add comment regarding sse* insns and prefixes.
+
+2009-02-03 Sandip Matte <sandip@rmicorp.com>
+
+ * mips.h (INSN_XLR): Define.
+ (INSN_CHIP_MASK): Update.
+ (CPU_XLR): Define.
+ (OPCODE_IS_MEMBER): Update.
+ (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
+
+2009-01-28 Doug Evans <dje@google.com>
+
+ * opcode/i386.h: Add multiple inclusion protection.
+ (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
+ (EDI_REG_NUM): New macros.
+ (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
+ (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
+ (REX_PREFIX_P): New macro.
+
+2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (struct powerpc_opcode): New field "deprecated".
+ (PPC_OPCODE_NOPOWER4): Delete.
+
2008-11-28 Joshua Kinard <kumba@gentoo.org>
* mips.h: Define CPU_R14000, CPU_R16000.
PR 3134
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
with a 32-bit displacement but without the top bit of the 4th byte
- set.
+ set.
2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
* ppc.h (PPC_OPCODE_CELL): Define.
-
+
2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
- * i386.h : Modify opcode to support for the change in POPCNT opcode
+ * i386.h : Modify opcode to support for the change in POPCNT opcode
in amdfam10 architecture.
2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
2006-06-05 Thiemo Seufer <ths@mips.com>
- * mips.h: Improve description of MT flags.
+ * mips.h: Improve description of MT flags.
2006-05-25 Richard Sandiford <richard@codesourcery.com>