/* AArch64 assembler/disassembler support.
- Copyright (C) 2009-2020 Free Software Foundation, Inc.
+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GNU Binutils.
#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
-#define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */
#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */
#define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */
#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
-#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */
+#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* v8.5 Flag Manipulation version 2. */
#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
#define AARCH64_FEATURE_F32MM (1ULL << 53)
#define AARCH64_FEATURE_F64MM (1ULL << 54)
+#define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */
/* Crypto instructions are the combination of AES and SHA2. */
#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
AARCH64_FEATURE_V8_4 \
| AARCH64_FEATURE_DOTPROD \
+ | AARCH64_FEATURE_FLAGM \
| AARCH64_FEATURE_F16_FML)
#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
AARCH64_FEATURE_V8_5 \
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
- AARCH64_OPND_CSRE_CSR, /* CSRE CSR instruction Rt field. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
static inline bfd_boolean
alias_opcode_p (const aarch64_opcode *opcode)
{
- return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
+ return (opcode->flags & F_ALIAS) != 0;
}
static inline bfd_boolean
opcode_has_alias (const aarch64_opcode *opcode)
{
- return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
+ return (opcode->flags & F_HAS_ALIAS) != 0;
}
/* Priority for disassembling preference. */
static inline bfd_boolean
pseudo_opcode_p (const aarch64_opcode *opcode)
{
- return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
+ return (opcode->flags & F_PSEUDO) != 0lu;
}
static inline bfd_boolean
optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
{
- return (((opcode->flags >> 12) & 0x7) == idx + 1)
- ? TRUE : FALSE;
+ return ((opcode->flags >> 12) & 0x7) == idx + 1;
}
static inline aarch64_insn
opcode_has_special_coder (const aarch64_opcode *opcode)
{
return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
- | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
- : FALSE;
+ | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0;
}
\f
struct aarch64_name_value_pair
{
/* The instruction that caused this sequence to be opened. */
aarch64_inst *instr;
- /* The number of instructions the above instruction allows to be kept in the
+ /* The number of instructions the above instruction allows one to be kept in the
sequence before an automatic close is done. */
int num_insns;
/* The instructions currently added to the sequence. */
/* Encoding entrypoint. */
-extern int
+extern bfd_boolean
aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
aarch64_insn *, aarch64_opnd_qualifier_t *,
aarch64_operand_error *, aarch64_instr_sequence *);