TRUE/FALSE simplification

[binutils-gdb.git] / include / opcode / aarch64.h

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index efa265717ada2ca7327467fecd73027c02b2766c..e48bea6db6ec271195b9d31f5441d4abda48181f 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1,6 +1,6 @@
 /* AArch64 assembler/disassembler support.
 
-   Copyright (C) 2009-2020 Free Software Foundation, Inc.
+   Copyright (C) 2009-2021 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of GNU Binutils.
@@ -51,8 +51,8 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_V8_4        (1ULL << 11) /* ARMv8.4 processors.  */
 #define AARCH64_FEATURE_V8_R        (1ULL << 12) /* Armv8-R processors.  */
 #define AARCH64_FEATURE_V8_7        (1ULL << 13) /* Armv8.7 processors.  */
-#define AARCH64_FEATURE_CSRE        (1ULL << 14) /* CSRE feature.  */
 #define AARCH64_FEATURE_LS64        (1ULL << 15) /* Atomic 64-byte load/store.  */
+#define AARCH64_FEATURE_PAC         (1ULL << 16) /* v8.3 Pointer Authentication.  */
 #define AARCH64_FEATURE_FP          (1ULL << 17) /* FP instructions.  */
 #define AARCH64_FEATURE_SIMD        (1ULL << 18) /* SIMD instructions.  */
 #define AARCH64_FEATURE_CRC         (1ULL << 19) /* CRC instructions.  */
@@ -74,7 +74,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_AES         (1ULL << 35) /* AES instructions.  */
 #define AARCH64_FEATURE_F16_FML      (1ULL << 36) /* v8.2 FP16FML ins.  */
 #define AARCH64_FEATURE_V8_5        (1ULL << 37) /* ARMv8.5 processors.  */
-#define AARCH64_FEATURE_FLAGMANIP    (1ULL << 38) /* Flag Manipulation insns.  */
+#define AARCH64_FEATURE_FLAGMANIP    (1ULL << 38) /* v8.5 Flag Manipulation version 2.  */
 #define AARCH64_FEATURE_FRINTTS      (1ULL << 39) /* FRINT[32,64][Z,X] insns.  */
 #define AARCH64_FEATURE_SB          (1ULL << 40) /* SB instruction.  */
 #define AARCH64_FEATURE_PREDRES      (1ULL << 41) /* Execution and Data Prediction Restriction instructions.  */
@@ -89,6 +89,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_I8MM        (1ULL << 52) /* Matrix Multiply instructions.  */
 #define AARCH64_FEATURE_F32MM       (1ULL << 53)
 #define AARCH64_FEATURE_F64MM       (1ULL << 54)
+#define AARCH64_FEATURE_FLAGM       (1ULL << 55) /* v8.4 Flag Manipulation.  */
 
 /* Crypto instructions are the combination of AES and SHA2.  */
 #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
@@ -110,11 +111,13 @@ typedef uint32_t aarch64_insn;
                                                 AARCH64_FEATURE_V8_2)
 #define AARCH64_ARCH_V8_3      AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
                                                 AARCH64_FEATURE_V8_3   \
+                                                | AARCH64_FEATURE_PAC  \
                                                 | AARCH64_FEATURE_RCPC \
                                                 | AARCH64_FEATURE_COMPNUM)
 #define AARCH64_ARCH_V8_4      AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
                                                 AARCH64_FEATURE_V8_4   \
                                                 | AARCH64_FEATURE_DOTPROD \
+                                                | AARCH64_FEATURE_FLAGM \
                                                 | AARCH64_FEATURE_F16_FML)
 #define AARCH64_ARCH_V8_5      AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
                                                 AARCH64_FEATURE_V8_5   \
@@ -199,6 +202,7 @@ enum aarch64_opnd
   AARCH64_OPND_Rm,     /* Integer register as source.  */
   AARCH64_OPND_Rt,     /* Integer register used in ld/st instructions.  */
   AARCH64_OPND_Rt2,    /* Integer register used in ld/st pair instructions.  */
+  AARCH64_OPND_Rt_LS64,        /* Integer register used in LS64 instructions.  */
   AARCH64_OPND_Rt_SP,  /* Integer Rt or SP used in STG instructions.  */
   AARCH64_OPND_Rs,     /* Integer register used in ld/st exclusive.  */
   AARCH64_OPND_Ra,     /* Integer register used in ddp_3src instructions.  */
@@ -435,7 +439,6 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_ZtxN,       /* SVE vector register list in Zt.  */
   AARCH64_OPND_TME_UIMM16,     /* TME unsigned 16-bit immediate.  */
   AARCH64_OPND_SM3_IMM2,       /* SM3 encodes lane in bits [13, 14].  */
-  AARCH64_OPND_CSRE_CSR,       /* CSRE CSR instruction Rt field.  */
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an
@@ -897,13 +900,13 @@ extern aarch64_opcode aarch64_opcode_table[];
 static inline bfd_boolean
 alias_opcode_p (const aarch64_opcode *opcode)
 {
-  return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
+  return (opcode->flags & F_ALIAS) != 0;
 }
 
 static inline bfd_boolean
 opcode_has_alias (const aarch64_opcode *opcode)
 {
-  return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
+  return (opcode->flags & F_HAS_ALIAS) != 0;
 }
 
 /* Priority for disassembling preference.  */
@@ -916,14 +919,13 @@ opcode_priority (const aarch64_opcode *opcode)
 static inline bfd_boolean
 pseudo_opcode_p (const aarch64_opcode *opcode)
 {
-  return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
+  return (opcode->flags & F_PSEUDO) != 0lu;
 }
 
 static inline bfd_boolean
 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 {
-  return (((opcode->flags >> 12) & 0x7) == idx + 1)
-    ? TRUE : FALSE;
+  return ((opcode->flags >> 12) & 0x7) == idx + 1;
 }
 
 static inline aarch64_insn
@@ -942,8 +944,7 @@ static inline bfd_boolean
 opcode_has_special_coder (const aarch64_opcode *opcode)
 {
   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
-         | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
-    : FALSE;
+         | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0;
 }
 \f
 struct aarch64_name_value_pair
@@ -1250,7 +1251,7 @@ struct aarch64_instr_sequence
 {
   /* The instruction that caused this sequence to be opened.  */
   aarch64_inst *instr;
-  /* The number of instructions the above instruction allows to be kept in the
+  /* The number of instructions the above instruction allows one to be kept in the
      sequence before an automatic close is done.  */
   int num_insns;
   /* The instructions currently added to the sequence.  */
@@ -1261,7 +1262,7 @@ struct aarch64_instr_sequence
 
 /* Encoding entrypoint.  */
 
-extern int
+extern bfd_boolean
 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
                       aarch64_insn *, aarch64_opnd_qualifier_t *,
                       aarch64_operand_error *, aarch64_instr_sequence *);