/* mips.h. Mips opcode list for GDB, the GNU debugger.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2003, 2004, 2005
Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef _MIPS_H_
#define _MIPS_H_
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
#define OP_SH_CODE19 6 /* 19 bit wait code. */
#define OP_MASK_CODE19 0x7ffff
+#define OP_SH_ALN 21
+#define OP_MASK_ALN 0x7
+#define OP_SH_VSEL 21
+#define OP_MASK_VSEL 0x1f
+#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
+ but 0x8-0xf don't select bytes. */
+#define OP_SH_VECBYTE 22
+#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
+#define OP_SH_VECALIGN 21
+#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
+#define OP_SH_INSMSB 11
+#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
+#define OP_SH_EXTMSBD 11
+
+/* MIPS DSP ASE */
+#define OP_SH_DSPACC 11
+#define OP_MASK_DSPACC 0x3
+#define OP_SH_DSPACC_S 21
+#define OP_MASK_DSPACC_S 0x3
+#define OP_SH_DSPSFT 20
+#define OP_MASK_DSPSFT 0x3f
+#define OP_SH_DSPSFT_7 19
+#define OP_MASK_DSPSFT_7 0x7f
+#define OP_SH_SA3 21
+#define OP_MASK_SA3 0x7
+#define OP_SH_SA4 21
+#define OP_MASK_SA4 0xf
+#define OP_SH_IMM8 16
+#define OP_MASK_IMM8 0xff
+#define OP_SH_IMM10 16
+#define OP_MASK_IMM10 0x3ff
+#define OP_SH_WRDSP 11
+#define OP_MASK_WRDSP 0x3f
+#define OP_SH_RDDSP 16
+#define OP_MASK_RDDSP 0x3f
+
+/* MIPS MT ASE */
+#define OP_SH_MT_U 5
+#define OP_MASK_MT_U 0x1
+#define OP_SH_MT_H 4
+#define OP_MASK_MT_H 0x1
+#define OP_SH_MTACC_T 18
+#define OP_MASK_MTACC_T 0x3
+#define OP_SH_MTACC_D 13
+#define OP_MASK_MTACC_D 0x3
+
+#define OP_OP_COP0 0x10
+#define OP_OP_COP1 0x11
+#define OP_OP_COP2 0x12
+#define OP_OP_COP3 0x13
+#define OP_OP_LWC1 0x31
+#define OP_OP_LWC2 0x32
+#define OP_OP_LWC3 0x33 /* a.k.a. pref */
+#define OP_OP_LDC1 0x35
+#define OP_OP_LDC2 0x36
+#define OP_OP_LDC3 0x37 /* a.k.a. ld */
+#define OP_OP_SWC1 0x39
+#define OP_OP_SWC2 0x3a
+#define OP_OP_SWC3 0x3b
+#define OP_OP_SDC1 0x3d
+#define OP_OP_SDC2 0x3e
+#define OP_OP_SDC3 0x3f /* a.k.a. sd */
+
+/* Values in the 'VSEL' field. */
+#define MDMX_FMTSEL_IMM_QH 0x1d
+#define MDMX_FMTSEL_IMM_OB 0x1e
+#define MDMX_FMTSEL_VEC_QH 0x15
+#define MDMX_FMTSEL_VEC_OB 0x16
+
+/* UDI */
+#define OP_SH_UDI1 6
+#define OP_MASK_UDI1 0x1f
+#define OP_SH_UDI2 6
+#define OP_MASK_UDI2 0x3ff
+#define OP_SH_UDI3 6
+#define OP_MASK_UDI3 0x7fff
+#define OP_SH_UDI4 6
+#define OP_MASK_UDI4 0xfffff
/* This structure holds information for a particular instruction. */
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
+ /* A collection of additional bits describing the instruction. */
+ unsigned long pinfo2;
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
};
-/* These are the characters which may appears in the args field of an
+/* These are the characters which may appear in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
+ Also used for immediate operands in vr5400 vector insns.
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
"q" 10 bit extra breakpoint code (OP_*_CODE2)
"J" 19 bit wait function code (OP_*_CODE19)
"x" accept and ignore register name
"z" must be zero register
+ "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
+ "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
+ LSB (OP_*_SHAMT).
+ Enforces: 0 <= pos < 32.
+ "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ (Also used by "dext" w/ different limits, but limits for
+ that are checked by the M_DEXT macro.)
+ "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
+ Enforces: 32 <= pos < 64.
+ "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
+ "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
+ "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
+ Requires that "+A" or "+E" occur first to set position.
+ Enforces: 32 < (pos+size) <= 64.
Floating point instructions:
"D" 5 bit destination register (OP_*_FD)
"G" 5 bit destination register (OP_*_RD)
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
+ "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
+ "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
+ see also "k" above
+ "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
+ for pretty-printing in disassembly only.
Macro instructions:
"A" General 32 bit expression
- "I" 32 bit immediate
+ "I" 32 bit immediate (value placed in imm_expr).
+ "+I" 32 bit immediate (value placed in imm2_expr).
"F" 64 bit floating point constant in .rdata
"L" 64 bit floating point constant in .lit8
"f" 32 bit floating point constant
"l" 32 bit floating point constant in .lit4
+ MDMX instruction operands (note that while these use the FP register
+ fields, they accept both $fN and $vN names for the registers):
+ "O" MDMX alignment offset (OP_*_ALN)
+ "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
+ "X" MDMX destination register (OP_*_FD)
+ "Y" MDMX source register (OP_*_FS)
+ "Z" MDMX source register (OP_*_FT)
+
+ DSP ASE usage:
+ "3" 3 bit unsigned immediate (OP_*_SA3)
+ "4" 4 bit unsigned immediate (OP_*_SA4)
+ "5" 8 bit unsigned immediate (OP_*_IMM8)
+ "6" 5 bit unsigned immediate (OP_*_RS)
+ "7" 2 bit dsp accumulator register (OP_*_DSPACC)
+ "8" 6 bit unsigned immediate (OP_*_WRDSP)
+ "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
+ "0" 6 bit signed immediate (OP_*_DSPSFT)
+ ":" 7 bit signed immediate (OP_*_DSPSFT_7)
+ "'" 6 bit unsigned immediate (OP_*_RDDSP)
+ "@" 10 bit signed immediate (OP_*_IMM10)
+
+ MT ASE usage:
+ "!" 1 bit immediate at bit 5
+ "$" 1 bit immediate at bit 4
+ "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
+ "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
+ "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
+ "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
+ "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
+
+ UDI immediates:
+ "+1" UDI immediate bits 6-10
+ "+2" UDI immediate bits 6-15
+ "+3" UDI immediate bits 6-20
+ "+4" UDI immediate bits 6-25
+
Other:
"()" parens surrounding optional value
"," separates operands
+ "[]" brackets around index for vector-op scalar operand specifier (vr5400)
+ "+" Start of extension sequence.
Characters used so far, for quick reference when adding more:
- "<>(),"
- "ABCDEFGHIJLMNPRSTUVW"
- "abcdfhijklopqrstuvwxz"
+ "34567890"
+ "%[]<>(),+:'@!$*&"
+ "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
+ "abcdefghijklopqrstuvwxz"
+
+ Extension character sequences used so far ("+" followed by the
+ following), for quick reference when adding more:
+ "1234"
+ "ABCDEFGHIT"
+ "t"
*/
/* These are the bits which may be set in the pinfo field of an
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
+/* These are the bits which may be set in the pinfo2 field of an
+ instruction. */
+
+/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
+#define INSN2_ALIAS 0x00000001
+/* Instruction reads MDMX accumulator. */
+#define INSN2_READ_MDMX_ACC 0x00000002
+/* Instruction writes MDMX accumulator. */
+#define INSN2_WRITE_MDMX_ACC 0x00000004
+
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. ISAs, as defined below, are logical
- ORs of these bits, indicatingthat they support the instructions
+ ORs of these bits, indicating that they support the instructions
defined at the given level. */
#define INSN_ISA_MASK 0x00000fff
-#define INSN_ISA1 0x00000010
-#define INSN_ISA2 0x00000020
-#define INSN_ISA3 0x00000040
-#define INSN_ISA4 0x00000080
-#define INSN_ISA5 0x00000100
-#define INSN_ISA32 0x00000200
-#define INSN_ISA64 0x00000400
+#define INSN_ISA1 0x00000001
+#define INSN_ISA2 0x00000002
+#define INSN_ISA3 0x00000004
+#define INSN_ISA4 0x00000008
+#define INSN_ISA5 0x00000010
+#define INSN_ISA32 0x00000020
+#define INSN_ISA64 0x00000040
+#define INSN_ISA32R2 0x00000080
+#define INSN_ISA64R2 0x00000100
+
+/* Masks used for MIPS-defined ASEs. */
+#define INSN_ASE_MASK 0x0c00f000
+
+/* DSP ASE */
+#define INSN_DSP 0x00001000
+/* MIPS 16 ASE */
+#define INSN_MIPS16 0x00002000
+/* MIPS-3D ASE */
+#define INSN_MIPS3D 0x00004000
+/* MDMX ASE */
+#define INSN_MDMX 0x00008000
/* Chip specific instructions. These are bitmasks. */
#define INSN_10000 0x00100000
/* Broadcom SB-1 instruction. */
#define INSN_SB1 0x00200000
+/* NEC VR4111/VR4181 instruction. */
+#define INSN_4111 0x00400000
+/* NEC VR4120 instruction. */
+#define INSN_4120 0x00800000
+/* NEC VR5400 instruction. */
+#define INSN_5400 0x01000000
+/* NEC VR5500 instruction. */
+#define INSN_5500 0x02000000
+
+/* MT ASE */
+#define INSN_MT 0x04000000
+
+/* SmartMIPS ASE. */
+#define INSN_SMARTMIPS 0x08000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
+
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
+#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
+#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
+
+
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
#define CPU_UNKNOWN 0 /* Gas internal use. */
-#define CPU_R2000 2000
#define CPU_R3000 3000
#define CPU_R3900 3900
#define CPU_R4000 4000
#define CPU_R4010 4010
#define CPU_VR4100 4100
#define CPU_R4111 4111
+#define CPU_VR4120 4120
#define CPU_R4300 4300
#define CPU_R4400 4400
#define CPU_R4600 4600
#define CPU_R4650 4650
#define CPU_R5000 5000
+#define CPU_VR5400 5400
+#define CPU_VR5500 5500
#define CPU_R6000 6000
+#define CPU_RM7000 7000
#define CPU_R8000 8000
+#define CPU_RM9000 9000
#define CPU_R10000 10000
#define CPU_R12000 12000
#define CPU_MIPS16 16
#define CPU_MIPS32 32
+#define CPU_MIPS32R2 33
#define CPU_MIPS5 5
#define CPU_MIPS64 64
+#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
-/* Test for membership in an ISA including chip specific ISAs.
- INSN is pointer to an element of the opcode table; ISA is the
- specified ISA to test against; and CPU is the CPU specific ISA
- to test, or zero if no CPU specific ISA test is desired. */
+/* Test for membership in an ISA including chip specific ISAs. INSN
+ is pointer to an element of the opcode table; ISA is the specified
+ ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
+ test, or zero if no CPU specific ISA test is desired. */
#define OPCODE_IS_MEMBER(insn, isa, cpu) \
(((insn)->membership & isa) != 0 \
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
+ || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
+ || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
- || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
- && ((insn)->membership & INSN_4100) != 0) \
+ || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
&& ((insn)->membership & INSN_10000) != 0) \
- || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0))
+ || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
+ || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
+ || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
+ || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
+ || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
+ || 0) /* Please keep this term for easier source merging. */
/* This is a list of macro expanded instructions.
M_BNE,
M_BNE_I,
M_BNEL_I,
+ M_CACHE_AB,
M_DABS,
M_DADD_I,
M_DADDU_I,
M_DDIV_3I,
M_DDIVU_3,
M_DDIVU_3I,
+ M_DEXT,
+ M_DINS,
M_DIV_3,
M_DIV_3I,
M_DIVU_3,
M_DIVU_3I,
M_DLA_AB,
+ M_DLCA_AB,
M_DLI,
M_DMUL,
M_DMUL_I,
M_LB_AB,
M_LBU_A,
M_LBU_AB,
+ M_LCA_AB,
M_LD_A,
M_LD_OB,
M_LD_AB,
M_REM_3I,
M_REMU_3,
M_REMU_3I,
+ M_DROL,
M_ROL,
+ M_DROL_I,
M_ROL_I,
+ M_DROR,
M_ROR,
+ M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
- */
+ "m" 7 bit register list for save instruction (18 bit extended)
+ "M" 7 bit register list for restore instruction (18 bit extended)
+ */
+
+/* Save/restore encoding for the args field when all 4 registers are
+ either saved as arguments or saved/restored as statics. */
+#define MIPS16_ALL_ARGS 0xe
+#define MIPS16_ALL_STATICS 0xb
/* For the mips16, we use the same opcode table format and a few of
the same flags. However, most of the flags are different. */
projects / binutils-gdb.git / blobdiff