/* ppc.h -- Header file for PowerPC opcode table
- Copyright (C) 1994-2016 Free Software Foundation, Inc.
+ Copyright (C) 1994-2017 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
/* Values defined for the flags field of a struct powerpc_opcode. */
/* Opcode is defined for the PowerPC architecture. */
-#define PPC_OPCODE_PPC 1
+#define PPC_OPCODE_PPC 0x1ull
/* Opcode is defined for the POWER (RS/6000) architecture. */
-#define PPC_OPCODE_POWER 2
+#define PPC_OPCODE_POWER 0x2ull
/* Opcode is defined for the POWER2 (Rios 2) architecture. */
-#define PPC_OPCODE_POWER2 4
+#define PPC_OPCODE_POWER2 0x4ull
/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
but it also supports many additional POWER instructions. */
-#define PPC_OPCODE_601 8
+#define PPC_OPCODE_601 0x8ull
/* Opcode is supported in both the Power and PowerPC architectures
(ie, compiler's -mcpu=common or assembler's -mcom). More than just
the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
and PPC_OPCODE_POWER2 because many instructions changed mnemonics
between POWER and POWERPC. */
-#define PPC_OPCODE_COMMON 0x10
+#define PPC_OPCODE_COMMON 0x10ull
/* Opcode is supported for any Power or PowerPC platform (this is
for the assembler's -many option, and it eliminates duplicates). */
-#define PPC_OPCODE_ANY 0x20
+#define PPC_OPCODE_ANY 0x20ull
/* Opcode is only defined on 64 bit architectures. */
-#define PPC_OPCODE_64 0x40
+#define PPC_OPCODE_64 0x40ull
/* Opcode is supported as part of the 64-bit bridge. */
-#define PPC_OPCODE_64_BRIDGE 0x80
+#define PPC_OPCODE_64_BRIDGE 0x80ull
/* Opcode is supported by Altivec Vector Unit */
-#define PPC_OPCODE_ALTIVEC 0x100
+#define PPC_OPCODE_ALTIVEC 0x100ull
/* Opcode is supported by PowerPC 403 processor. */
-#define PPC_OPCODE_403 0x200
+#define PPC_OPCODE_403 0x200ull
/* Opcode is supported by PowerPC BookE processor. */
-#define PPC_OPCODE_BOOKE 0x400
+#define PPC_OPCODE_BOOKE 0x400ull
/* Opcode is supported by PowerPC 440 processor. */
-#define PPC_OPCODE_440 0x800
+#define PPC_OPCODE_440 0x800ull
/* Opcode is only supported by Power4 architecture. */
-#define PPC_OPCODE_POWER4 0x1000
+#define PPC_OPCODE_POWER4 0x1000ull
/* Opcode is only supported by Power7 architecture. */
-#define PPC_OPCODE_POWER7 0x2000
+#define PPC_OPCODE_POWER7 0x2000ull
/* Opcode is only supported by e500x2 Core. */
-#define PPC_OPCODE_SPE 0x4000
+#define PPC_OPCODE_SPE 0x4000ull
/* Opcode is supported by e500x2 Integer select APU. */
-#define PPC_OPCODE_ISEL 0x8000
+#define PPC_OPCODE_ISEL 0x8000ull
/* Opcode is an e500 SPE floating point instruction. */
-#define PPC_OPCODE_EFS 0x10000
+#define PPC_OPCODE_EFS 0x10000ull
/* Opcode is supported by branch locking APU. */
-#define PPC_OPCODE_BRLOCK 0x20000
+#define PPC_OPCODE_BRLOCK 0x20000ull
/* Opcode is supported by performance monitor APU. */
-#define PPC_OPCODE_PMR 0x40000
+#define PPC_OPCODE_PMR 0x40000ull
/* Opcode is supported by cache locking APU. */
-#define PPC_OPCODE_CACHELCK 0x80000
+#define PPC_OPCODE_CACHELCK 0x80000ull
/* Opcode is supported by machine check APU. */
-#define PPC_OPCODE_RFMCI 0x100000
+#define PPC_OPCODE_RFMCI 0x100000ull
/* Opcode is only supported by Power5 architecture. */
-#define PPC_OPCODE_POWER5 0x200000
+#define PPC_OPCODE_POWER5 0x200000ull
/* Opcode is supported by PowerPC e300 family. */
-#define PPC_OPCODE_E300 0x400000
+#define PPC_OPCODE_E300 0x400000ull
/* Opcode is only supported by Power6 architecture. */
-#define PPC_OPCODE_POWER6 0x800000
+#define PPC_OPCODE_POWER6 0x800000ull
/* Opcode is only supported by PowerPC Cell family. */
-#define PPC_OPCODE_CELL 0x1000000
+#define PPC_OPCODE_CELL 0x1000000ull
/* Opcode is supported by CPUs with paired singles support. */
-#define PPC_OPCODE_PPCPS 0x2000000
+#define PPC_OPCODE_PPCPS 0x2000000ull
/* Opcode is supported by Power E500MC */
-#define PPC_OPCODE_E500MC 0x4000000
+#define PPC_OPCODE_E500MC 0x4000000ull
/* Opcode is supported by PowerPC 405 processor. */
-#define PPC_OPCODE_405 0x8000000
+#define PPC_OPCODE_405 0x8000000ull
/* Opcode is supported by Vector-Scalar (VSX) Unit */
-#define PPC_OPCODE_VSX 0x10000000
+#define PPC_OPCODE_VSX 0x10000000ull
/* Opcode is supported by A2. */
-#define PPC_OPCODE_A2 0x20000000
+#define PPC_OPCODE_A2 0x20000000ull
/* Opcode is supported by PowerPC 476 processor. */
-#define PPC_OPCODE_476 0x40000000
+#define PPC_OPCODE_476 0x40000000ull
/* Opcode is supported by AppliedMicro Titan core */
-#define PPC_OPCODE_TITAN 0x80000000
+#define PPC_OPCODE_TITAN 0x80000000ull
/* Opcode which is supported by the e500 family */
#define PPC_OPCODE_E500 0x100000000ull
#define PPC_OPCODE_7450 0x8000000000ull
/* Opcode is supported by ppc821/850/860. */
-#define PPC_OPCODE_860 0x10000000000ull
+#define PPC_OPCODE_860 0x10000000000ull
/* Opcode is only supported by Power9 architecture. */
-#define PPC_OPCODE_POWER9 0x20000000000ull
+#define PPC_OPCODE_POWER9 0x20000000000ull
/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
-#define PPC_OPCODE_VSX3 0x40000000000ull
+#define PPC_OPCODE_VSX3 0x40000000000ull
- /* Opcode is supported by e200z4. */
-#define PPC_OPCODE_E200Z4 0x80000000000ull
+/* Opcode is supported by e200z4. */
+#define PPC_OPCODE_E200Z4 0x80000000000ull
+
+/* Disassemble to instructions matching later in the opcode table
+ with fewer "mask" bits set rather than the earlist match. Fewer
+ "mask" bits set imply a more general form of the opcode, in fact
+ the underlying machine instruction. */
+#define PPC_OPCODE_RAW 0x100000000000ull
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
goes in the insn. */
#define PPC_OPSHIFT_INV (-1U << 31)
-/* Values defined for the flags field of a struct powerpc_operand. */
+/* Values defined for the flags field of a struct powerpc_operand.
+ Keep the register bits low: They need to fit in an unsigned short. */
-/* This operand takes signed values. */
-#define PPC_OPERAND_SIGNED (0x1)
+/* This operand names a register. The disassembler uses this to print
+ register names with a leading 'r'. */
+#define PPC_OPERAND_GPR (0x1)
-/* This operand takes signed values, but also accepts a full positive
- range of values when running in 32 bit mode. That is, if bits is
- 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
- this flag is ignored. */
-#define PPC_OPERAND_SIGNOPT (0x2)
+/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
+#define PPC_OPERAND_GPR_0 (0x2)
-/* This operand does not actually exist in the assembler input. This
- is used to support extended mnemonics such as mr, for which two
- operands fields are identical. The assembler should call the
- insert function with any op value. The disassembler should call
- the extract function, ignore the return value, and check the value
- placed in the valid argument. */
-#define PPC_OPERAND_FAKE (0x4)
+/* This operand names a floating point register. The disassembler
+ prints these with a leading 'f'. */
+#define PPC_OPERAND_FPR (0x4)
-/* The next operand should be wrapped in parentheses rather than
- separated from this one by a comma. This is used for the load and
- store instructions which want their operands to look like
- reg,displacement(reg)
- */
-#define PPC_OPERAND_PARENS (0x8)
+/* This operand names a vector unit register. The disassembler
+ prints these with a leading 'v'. */
+#define PPC_OPERAND_VR (0x8)
+
+/* This operand names a vector-scalar unit register. The disassembler
+ prints these with a leading 'vs'. */
+#define PPC_OPERAND_VSR (0x10)
-/* This operand may use the symbolic names for the CR fields, which
- are
+/* This operand may use the symbolic names for the CR fields (even
+ without -mregnames), which are
lt 0 gt 1 eq 2 so 3 un 3
cr0 0 cr1 1 cr2 2 cr3 3
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
-#define PPC_OPERAND_CR_BIT (0x10)
+#define PPC_OPERAND_CR_BIT (0x20)
-/* This operand names a register. The disassembler uses this to print
- register names with a leading 'r'. */
-#define PPC_OPERAND_GPR (0x20)
+/* This is a CR FIELD that does not use symbolic names (unless
+ -mregnames is in effect). */
+#define PPC_OPERAND_CR_REG (0x40)
-/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
-#define PPC_OPERAND_GPR_0 (0x40)
+/* This operand names a special purpose register. */
+#define PPC_OPERAND_SPR (0x80)
-/* This operand names a floating point register. The disassembler
- prints these with a leading 'f'. */
-#define PPC_OPERAND_FPR (0x80)
+/* This operand names a paired-single graphics quantization register. */
+#define PPC_OPERAND_GQR (0x100)
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
-#define PPC_OPERAND_RELATIVE (0x100)
+#define PPC_OPERAND_RELATIVE (0x200)
/* This operand is an absolute branch address. The disassembler
prints these symbolically if possible. */
-#define PPC_OPERAND_ABSOLUTE (0x200)
+#define PPC_OPERAND_ABSOLUTE (0x400)
-/* This operand is optional, and is zero if omitted. This is used for
- example, in the optional BF field in the comparison instructions. The
- assembler must count the number of operands remaining on the line,
- and the number of operands remaining for the opcode, and decide
- whether this operand is present or not. The disassembler should
- print this operand out only if it is not zero. */
-#define PPC_OPERAND_OPTIONAL (0x400)
-
-/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
- is omitted, then for the next operand use this operand value plus
- 1, ignoring the next operand field for the opcode. This wretched
- hack is needed because the Power rotate instructions can take
- either 4 or 5 operands. The disassembler should print this operand
- out regardless of the PPC_OPERAND_OPTIONAL field. */
-#define PPC_OPERAND_NEXT (0x800)
+/* This operand takes signed values. */
+#define PPC_OPERAND_SIGNED (0x800)
-/* This operand should be regarded as a negative number for the
- purposes of overflow checking (i.e., the normal most negative
- number is disallowed and one more than the normal most positive
- number is allowed). This flag will only be set for a signed
- operand. */
-#define PPC_OPERAND_NEGATIVE (0x1000)
+/* This operand takes signed values, but also accepts a full positive
+ range of values when running in 32 bit mode. That is, if bits is
+ 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
+ this flag is ignored. */
+#define PPC_OPERAND_SIGNOPT (0x1000)
-/* This operand names a vector unit register. The disassembler
- prints these with a leading 'v'. */
-#define PPC_OPERAND_VR (0x2000)
+/* The next operand should be wrapped in parentheses rather than
+ separated from this one by a comma. This is used for the load and
+ store instructions which want their operands to look like
+ reg,displacement(reg)
+ */
+#define PPC_OPERAND_PARENS (0x2000)
/* This operand is for the DS field in a DS form instruction. */
#define PPC_OPERAND_DS (0x4000)
/* This operand is for the DQ field in a DQ form instruction. */
#define PPC_OPERAND_DQ (0x8000)
+/* This operand should be regarded as a negative number for the
+ purposes of overflow checking (i.e., the normal most negative
+ number is disallowed and one more than the normal most positive
+ number is allowed). This flag will only be set for a signed
+ operand. */
+#define PPC_OPERAND_NEGATIVE (0x10000)
+
/* Valid range of operand is 0..n rather than 0..n-1. */
-#define PPC_OPERAND_PLUS1 (0x10000)
+#define PPC_OPERAND_PLUS1 (0x20000)
-/* Xilinx APU and FSL related operands */
-#define PPC_OPERAND_FSL (0x20000)
-#define PPC_OPERAND_FCR (0x40000)
-#define PPC_OPERAND_UDI (0x80000)
+/* This operand does not actually exist in the assembler input. This
+ is used to support extended mnemonics such as mr, for which two
+ operands fields are identical. The assembler should call the
+ insert function with any op value. The disassembler should call
+ the extract function, ignore the return value, and check the value
+ placed in the valid argument. */
+#define PPC_OPERAND_FAKE (0x40000)
-/* This operand names a vector-scalar unit register. The disassembler
- prints these with a leading 'vs'. */
-#define PPC_OPERAND_VSR (0x100000)
+/* This operand is optional, and is zero if omitted. This is used for
+ example, in the optional BF field in the comparison instructions. The
+ assembler must count the number of operands remaining on the line,
+ and the number of operands remaining for the opcode, and decide
+ whether this operand is present or not. The disassembler should
+ print this operand out only if it is not zero. */
+#define PPC_OPERAND_OPTIONAL (0x80000)
-/* This is a CR FIELD that does not use symbolic names. */
-#define PPC_OPERAND_CR_REG (0x200000)
+/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
+ is omitted, then for the next operand use this operand value plus
+ 1, ignoring the next operand field for the opcode. This wretched
+ hack is needed because the Power rotate instructions can take
+ either 4 or 5 operands. The disassembler should print this operand
+ out regardless of the PPC_OPERAND_OPTIONAL field. */
+#define PPC_OPERAND_NEXT (0x100000)
/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
is omitted, then the value it should use for the operand is stored
in the SHIFT field of the immediatly following operand field. */
-#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
+#define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
only optional when generating 32-bit code. */
-#define PPC_OPERAND_OPTIONAL32 (0x800000)
+#define PPC_OPERAND_OPTIONAL32 (0x400000)
+
+/* Xilinx APU and FSL related operands */
+#define PPC_OPERAND_FSL (0x800000)
+#define PPC_OPERAND_FCR (0x1000000)
+#define PPC_OPERAND_UDI (0x2000000)
\f
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
projects / binutils-gdb.git / blobdiff