-/* Automatically generated by parse-opcodes. */
+/* riscv-opc.h. RISC-V instruction opcode and CSR macros.
+ Copyright (C) 2011-2021 Free Software Foundation, Inc.
+ Contributed by Andrew Waterman
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version
+ 3, or (at your option) any later version.
+
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
#ifndef RISCV_ENCODING_H
#define RISCV_ENCODING_H
+/* Instruction opcode macros. */
#define MATCH_SLLI_RV32 0x1013
#define MASK_SLLI_RV32 0xfe00707f
#define MATCH_SRLI_RV32 0x5013
#define MASK_SW 0x707f
#define MATCH_SD 0x3023
#define MASK_SD 0x707f
+#define MATCH_PAUSE 0x0100000f
+#define MASK_PAUSE 0xffffffff
#define MATCH_FENCE 0xf
#define MASK_FENCE 0x707f
#define MATCH_FENCE_I 0x100f
#define MASK_FCVT_Q_LU 0xfff0007f
#define MATCH_FMV_Q_X 0xf6000053
#define MASK_FMV_Q_X 0xfff0707f
+#define MATCH_CLZ 0x60001013
+#define MASK_CLZ 0xfff0707f
+#define MATCH_CTZ 0x60101013
+#define MASK_CTZ 0xfff0707f
+#define MATCH_CPOP 0x60201013
+#define MASK_CPOP 0xfff0707f
+#define MATCH_MIN 0xa004033
+#define MASK_MIN 0xfe00707f
+#define MATCH_MINU 0xa005033
+#define MASK_MINU 0xfe00707f
+#define MATCH_MAX 0xa006033
+#define MASK_MAX 0xfe00707f
+#define MATCH_MAXU 0xa007033
+#define MASK_MAXU 0xfe00707f
+#define MATCH_SEXT_B 0x60401013
+#define MASK_SEXT_B 0xfff0707f
+#define MATCH_SEXT_H 0x60501013
+#define MASK_SEXT_H 0xfff0707f
+#define MATCH_PACK 0x8004033
+#define MASK_PACK 0xfe00707f
+#define MATCH_PACKH 0x8007033
+#define MASK_PACKH 0xfe00707f
+#define MATCH_PACKW 0x800403b
+#define MASK_PACKW 0xfe00707f
+#define MATCH_ANDN 0x40007033
+#define MASK_ANDN 0xfe00707f
+#define MATCH_ORN 0x40006033
+#define MASK_ORN 0xfe00707f
+#define MATCH_XNOR 0x40004033
+#define MASK_XNOR 0xfe00707f
+#define MATCH_ROL 0x60001033
+#define MASK_ROL 0xfe00707f
+#define MATCH_ROR 0x60005033
+#define MASK_ROR 0xfe00707f
+#define MATCH_RORI 0x60005013
+#define MASK_RORI 0xfc00707f
+#define MATCH_GREVI 0x68005013
+#define MASK_GREVI 0xfc00707f
+#define MATCH_GORCI 0x28005013
+#define MASK_GORCI 0xfc00707f
+#define MATCH_SHFLI 0x8001013
+#define MASK_SHFLI 0xfe00707f
+#define MATCH_UNSHFLI 0x8005013
+#define MASK_UNSHFLI 0xfe00707f
+#define MATCH_CLZW 0x6000101b
+#define MASK_CLZW 0xfff0707f
+#define MATCH_CTZW 0x6010101b
+#define MASK_CTZW 0xfff0707f
+#define MATCH_CPOPW 0x6020101b
+#define MASK_CPOPW 0xfff0707f
+#define MATCH_ROLW 0x6000103b
+#define MASK_ROLW 0xfe00707f
+#define MATCH_RORW 0x6000503b
+#define MASK_RORW 0xfe00707f
+#define MATCH_RORIW 0x6000501b
+#define MASK_RORIW 0xfe00707f
+#define MATCH_SH1ADD 0x20002033
+#define MASK_SH1ADD 0xfe00707f
+#define MATCH_SH2ADD 0x20004033
+#define MASK_SH2ADD 0xfe00707f
+#define MATCH_SH3ADD 0x20006033
+#define MASK_SH3ADD 0xfe00707f
+#define MATCH_SH1ADD_UW 0x2000203b
+#define MASK_SH1ADD_UW 0xfe00707f
+#define MATCH_SH2ADD_UW 0x2000403b
+#define MASK_SH2ADD_UW 0xfe00707f
+#define MATCH_SH3ADD_UW 0x2000603b
+#define MASK_SH3ADD_UW 0xfe00707f
+#define MATCH_ADD_UW 0x800003b
+#define MASK_ADD_UW 0xfe00707f
+#define MATCH_SLLI_UW 0x800101b
+#define MASK_SLLI_UW 0xfc00707f
+#define MATCH_CLMUL 0xa001033
+#define MASK_CLMUL 0xfe00707f
+#define MATCH_CLMULH 0xa003033
+#define MASK_CLMULH 0xfe00707f
+#define MATCH_CLMULR 0xa002033
+#define MASK_CLMULR 0xfe00707f
+#define MATCH_XPERM4 0x28002033
+#define MASK_XPERM4 0xfe00707f
+#define MATCH_XPERM8 0x28004033
+#define MASK_XPERM8 0xfe00707f
+#define MATCH_BCLRI 0x48001013
+#define MASK_BCLRI 0xfc00707f
+#define MATCH_BSETI 0x28001013
+#define MASK_BSETI 0xfc00707f
+#define MATCH_BINVI 0x68001013
+#define MASK_BINVI 0xfc00707f
+#define MATCH_BEXTI 0x48005013
+#define MASK_BEXTI 0xfc00707f
+#define MATCH_BCLR 0x48001033
+#define MASK_BCLR 0xfe00707f
+#define MATCH_BSET 0x28001033
+#define MASK_BSET 0xfe00707f
+#define MATCH_BINV 0x68001033
+#define MASK_BINV 0xfe00707f
+#define MATCH_BEXT 0x48005033
+#define MASK_BEXT 0xfe00707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_FLD 0x3007
#define MASK_C_LDSP 0xe003
#define MATCH_C_SDSP 0xe002
#define MASK_C_SDSP 0xe003
-#define MATCH_CUSTOM0 0xb
-#define MASK_CUSTOM0 0x707f
-#define MATCH_CUSTOM0_RS1 0x200b
-#define MASK_CUSTOM0_RS1 0x707f
-#define MATCH_CUSTOM0_RS1_RS2 0x300b
-#define MASK_CUSTOM0_RS1_RS2 0x707f
-#define MATCH_CUSTOM0_RD 0x400b
-#define MASK_CUSTOM0_RD 0x707f
-#define MATCH_CUSTOM0_RD_RS1 0x600b
-#define MASK_CUSTOM0_RD_RS1 0x707f
-#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM1 0x2b
-#define MASK_CUSTOM1 0x707f
-#define MATCH_CUSTOM1_RS1 0x202b
-#define MASK_CUSTOM1_RS1 0x707f
-#define MATCH_CUSTOM1_RS1_RS2 0x302b
-#define MASK_CUSTOM1_RS1_RS2 0x707f
-#define MATCH_CUSTOM1_RD 0x402b
-#define MASK_CUSTOM1_RD 0x707f
-#define MATCH_CUSTOM1_RD_RS1 0x602b
-#define MASK_CUSTOM1_RD_RS1 0x707f
-#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM2 0x5b
-#define MASK_CUSTOM2 0x707f
-#define MATCH_CUSTOM2_RS1 0x205b
-#define MASK_CUSTOM2_RS1 0x707f
-#define MATCH_CUSTOM2_RS1_RS2 0x305b
-#define MASK_CUSTOM2_RS1_RS2 0x707f
-#define MATCH_CUSTOM2_RD 0x405b
-#define MASK_CUSTOM2_RD 0x707f
-#define MATCH_CUSTOM2_RD_RS1 0x605b
-#define MASK_CUSTOM2_RD_RS1 0x707f
-#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM3 0x7b
-#define MASK_CUSTOM3 0x707f
-#define MATCH_CUSTOM3_RS1 0x207b
-#define MASK_CUSTOM3_RS1 0x707f
-#define MATCH_CUSTOM3_RS1_RS2 0x307b
-#define MASK_CUSTOM3_RS1_RS2 0x707f
-#define MATCH_CUSTOM3_RD 0x407b
-#define MASK_CUSTOM3_RD 0x707f
-#define MATCH_CUSTOM3_RD_RS1 0x607b
-#define MASK_CUSTOM3_RD_RS1 0x707f
-#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
-/* Support CSR to priv spec 1.11. */
+#define MATCH_SM3P0 0x10801013
+#define MASK_SM3P0 0xfff0707f
+#define MATCH_SM3P1 0x10901013
+#define MASK_SM3P1 0xfff0707f
+#define MATCH_SHA256SUM0 0x10001013
+#define MASK_SHA256SUM0 0xfff0707f
+#define MATCH_SHA256SUM1 0x10101013
+#define MASK_SHA256SUM1 0xfff0707f
+#define MATCH_SHA256SIG0 0x10201013
+#define MASK_SHA256SIG0 0xfff0707f
+#define MATCH_SHA256SIG1 0x10301013
+#define MASK_SHA256SIG1 0xfff0707f
+#define MATCH_SHA512SUM0R 0x50000033
+#define MASK_SHA512SUM0R 0xfe00707f
+#define MATCH_SHA512SUM1R 0x52000033
+#define MASK_SHA512SUM1R 0xfe00707f
+#define MATCH_SHA512SIG0L 0x54000033
+#define MASK_SHA512SIG0L 0xfe00707f
+#define MATCH_SHA512SIG0H 0x5c000033
+#define MASK_SHA512SIG0H 0xfe00707f
+#define MATCH_SHA512SIG1L 0x56000033
+#define MASK_SHA512SIG1L 0xfe00707f
+#define MATCH_SHA512SIG1H 0x5e000033
+#define MASK_SHA512SIG1H 0xfe00707f
+#define MATCH_SM4ED 0x30000033
+#define MASK_SM4ED 0x3e00707f
+#define MATCH_SM4KS 0x34000033
+#define MASK_SM4KS 0x3e00707f
+#define MATCH_AES32ESMI 0x26000033
+#define MASK_AES32ESMI 0x3e00707f
+#define MATCH_AES32ESI 0x22000033
+#define MASK_AES32ESI 0x3e00707f
+#define MATCH_AES32DSMI 0x2e000033
+#define MASK_AES32DSMI 0x3e00707f
+#define MATCH_AES32DSI 0x2a000033
+#define MASK_AES32DSI 0x3e00707f
+#define MATCH_SHA512SUM0 0x10401013
+#define MASK_SHA512SUM0 0xfff0707f
+#define MATCH_SHA512SUM1 0x10501013
+#define MASK_SHA512SUM1 0xfff0707f
+#define MATCH_SHA512SIG0 0x10601013
+#define MASK_SHA512SIG0 0xfff0707f
+#define MATCH_SHA512SIG1 0x10701013
+#define MASK_SHA512SIG1 0xfff0707f
+#define MATCH_AES64KS1I 0x31001013
+#define MASK_AES64KS1I 0xff00707f
+#define MATCH_AES64IM 0x30001013
+#define MASK_AES64IM 0xfff0707f
+#define MATCH_AES64KS2 0x7e000033
+#define MASK_AES64KS2 0xfe00707f
+#define MATCH_AES64ESM 0x36000033
+#define MASK_AES64ESM 0xfe00707f
+#define MATCH_AES64ES 0x32000033
+#define MASK_AES64ES 0xfe00707f
+#define MATCH_AES64DSM 0x3e000033
+#define MASK_AES64DSM 0xfe00707f
+#define MATCH_AES64DS 0x3a000033
+#define MASK_AES64DS 0xfe00707f
+#define MATCH_VSETVL 0x80007057
+#define MASK_VSETVL 0xfe00707f
+#define MATCH_VSETIVLI 0xc0007057
+#define MASK_VSETIVLI 0xc000707f
+#define MATCH_VSETVLI 0x00007057
+#define MASK_VSETVLI 0x8000707f
+#define MATCH_VLMV 0x02b00007
+#define MASK_VLMV 0xfff0707f
+#define MATCH_VSMV 0x02b00027
+#define MASK_VSMV 0xfff0707f
+#define MATCH_VLE8V 0x00000007
+#define MASK_VLE8V 0xfdf0707f
+#define MATCH_VLE16V 0x00005007
+#define MASK_VLE16V 0xfdf0707f
+#define MATCH_VLE32V 0x00006007
+#define MASK_VLE32V 0xfdf0707f
+#define MATCH_VLE64V 0x00007007
+#define MASK_VLE64V 0xfdf0707f
+#define MATCH_VSE8V 0x00000027
+#define MASK_VSE8V 0xfdf0707f
+#define MATCH_VSE16V 0x00005027
+#define MASK_VSE16V 0xfdf0707f
+#define MATCH_VSE32V 0x00006027
+#define MASK_VSE32V 0xfdf0707f
+#define MATCH_VSE64V 0x00007027
+#define MASK_VSE64V 0xfdf0707f
+#define MATCH_VLSE8V 0x08000007
+#define MASK_VLSE8V 0xfc00707f
+#define MATCH_VLSE16V 0x08005007
+#define MASK_VLSE16V 0xfc00707f
+#define MATCH_VLSE32V 0x08006007
+#define MASK_VLSE32V 0xfc00707f
+#define MATCH_VLSE64V 0x08007007
+#define MASK_VLSE64V 0xfc00707f
+#define MATCH_VSSE8V 0x08000027
+#define MASK_VSSE8V 0xfc00707f
+#define MATCH_VSSE16V 0x08005027
+#define MASK_VSSE16V 0xfc00707f
+#define MATCH_VSSE32V 0x08006027
+#define MASK_VSSE32V 0xfc00707f
+#define MATCH_VSSE64V 0x08007027
+#define MASK_VSSE64V 0xfc00707f
+#define MATCH_VLOXEI8V 0x0c000007
+#define MASK_VLOXEI8V 0xfc00707f
+#define MATCH_VLOXEI16V 0x0c005007
+#define MASK_VLOXEI16V 0xfc00707f
+#define MATCH_VLOXEI32V 0x0c006007
+#define MASK_VLOXEI32V 0xfc00707f
+#define MATCH_VLOXEI64V 0x0c007007
+#define MASK_VLOXEI64V 0xfc00707f
+#define MATCH_VSOXEI8V 0x0c000027
+#define MASK_VSOXEI8V 0xfc00707f
+#define MATCH_VSOXEI16V 0x0c005027
+#define MASK_VSOXEI16V 0xfc00707f
+#define MATCH_VSOXEI32V 0x0c006027
+#define MASK_VSOXEI32V 0xfc00707f
+#define MATCH_VSOXEI64V 0x0c007027
+#define MASK_VSOXEI64V 0xfc00707f
+#define MATCH_VLUXEI8V 0x04000007
+#define MASK_VLUXEI8V 0xfc00707f
+#define MATCH_VLUXEI16V 0x04005007
+#define MASK_VLUXEI16V 0xfc00707f
+#define MATCH_VLUXEI32V 0x04006007
+#define MASK_VLUXEI32V 0xfc00707f
+#define MATCH_VLUXEI64V 0x04007007
+#define MASK_VLUXEI64V 0xfc00707f
+#define MATCH_VSUXEI8V 0x04000027
+#define MASK_VSUXEI8V 0xfc00707f
+#define MATCH_VSUXEI16V 0x04005027
+#define MASK_VSUXEI16V 0xfc00707f
+#define MATCH_VSUXEI32V 0x04006027
+#define MASK_VSUXEI32V 0xfc00707f
+#define MATCH_VSUXEI64V 0x04007027
+#define MASK_VSUXEI64V 0xfc00707f
+#define MATCH_VLE8FFV 0x01000007
+#define MASK_VLE8FFV 0xfdf0707f
+#define MATCH_VLE16FFV 0x01005007
+#define MASK_VLE16FFV 0xfdf0707f
+#define MATCH_VLE32FFV 0x01006007
+#define MASK_VLE32FFV 0xfdf0707f
+#define MATCH_VLE64FFV 0x01007007
+#define MASK_VLE64FFV 0xfdf0707f
+#define MATCH_VLSEG2E8V 0x20000007
+#define MASK_VLSEG2E8V 0xfdf0707f
+#define MATCH_VSSEG2E8V 0x20000027
+#define MASK_VSSEG2E8V 0xfdf0707f
+#define MATCH_VLSEG3E8V 0x40000007
+#define MASK_VLSEG3E8V 0xfdf0707f
+#define MATCH_VSSEG3E8V 0x40000027
+#define MASK_VSSEG3E8V 0xfdf0707f
+#define MATCH_VLSEG4E8V 0x60000007
+#define MASK_VLSEG4E8V 0xfdf0707f
+#define MATCH_VSSEG4E8V 0x60000027
+#define MASK_VSSEG4E8V 0xfdf0707f
+#define MATCH_VLSEG5E8V 0x80000007
+#define MASK_VLSEG5E8V 0xfdf0707f
+#define MATCH_VSSEG5E8V 0x80000027
+#define MASK_VSSEG5E8V 0xfdf0707f
+#define MATCH_VLSEG6E8V 0xa0000007
+#define MASK_VLSEG6E8V 0xfdf0707f
+#define MATCH_VSSEG6E8V 0xa0000027
+#define MASK_VSSEG6E8V 0xfdf0707f
+#define MATCH_VLSEG7E8V 0xc0000007
+#define MASK_VLSEG7E8V 0xfdf0707f
+#define MATCH_VSSEG7E8V 0xc0000027
+#define MASK_VSSEG7E8V 0xfdf0707f
+#define MATCH_VLSEG8E8V 0xe0000007
+#define MASK_VLSEG8E8V 0xfdf0707f
+#define MATCH_VSSEG8E8V 0xe0000027
+#define MASK_VSSEG8E8V 0xfdf0707f
+#define MATCH_VLSEG2E16V 0x20005007
+#define MASK_VLSEG2E16V 0xfdf0707f
+#define MATCH_VSSEG2E16V 0x20005027
+#define MASK_VSSEG2E16V 0xfdf0707f
+#define MATCH_VLSEG3E16V 0x40005007
+#define MASK_VLSEG3E16V 0xfdf0707f
+#define MATCH_VSSEG3E16V 0x40005027
+#define MASK_VSSEG3E16V 0xfdf0707f
+#define MATCH_VLSEG4E16V 0x60005007
+#define MASK_VLSEG4E16V 0xfdf0707f
+#define MATCH_VSSEG4E16V 0x60005027
+#define MASK_VSSEG4E16V 0xfdf0707f
+#define MATCH_VLSEG5E16V 0x80005007
+#define MASK_VLSEG5E16V 0xfdf0707f
+#define MATCH_VSSEG5E16V 0x80005027
+#define MASK_VSSEG5E16V 0xfdf0707f
+#define MATCH_VLSEG6E16V 0xa0005007
+#define MASK_VLSEG6E16V 0xfdf0707f
+#define MATCH_VSSEG6E16V 0xa0005027
+#define MASK_VSSEG6E16V 0xfdf0707f
+#define MATCH_VLSEG7E16V 0xc0005007
+#define MASK_VLSEG7E16V 0xfdf0707f
+#define MATCH_VSSEG7E16V 0xc0005027
+#define MASK_VSSEG7E16V 0xfdf0707f
+#define MATCH_VLSEG8E16V 0xe0005007
+#define MASK_VLSEG8E16V 0xfdf0707f
+#define MATCH_VSSEG8E16V 0xe0005027
+#define MASK_VSSEG8E16V 0xfdf0707f
+#define MATCH_VLSEG2E32V 0x20006007
+#define MASK_VLSEG2E32V 0xfdf0707f
+#define MATCH_VSSEG2E32V 0x20006027
+#define MASK_VSSEG2E32V 0xfdf0707f
+#define MATCH_VLSEG3E32V 0x40006007
+#define MASK_VLSEG3E32V 0xfdf0707f
+#define MATCH_VSSEG3E32V 0x40006027
+#define MASK_VSSEG3E32V 0xfdf0707f
+#define MATCH_VLSEG4E32V 0x60006007
+#define MASK_VLSEG4E32V 0xfdf0707f
+#define MATCH_VSSEG4E32V 0x60006027
+#define MASK_VSSEG4E32V 0xfdf0707f
+#define MATCH_VLSEG5E32V 0x80006007
+#define MASK_VLSEG5E32V 0xfdf0707f
+#define MATCH_VSSEG5E32V 0x80006027
+#define MASK_VSSEG5E32V 0xfdf0707f
+#define MATCH_VLSEG6E32V 0xa0006007
+#define MASK_VLSEG6E32V 0xfdf0707f
+#define MATCH_VSSEG6E32V 0xa0006027
+#define MASK_VSSEG6E32V 0xfdf0707f
+#define MATCH_VLSEG7E32V 0xc0006007
+#define MASK_VLSEG7E32V 0xfdf0707f
+#define MATCH_VSSEG7E32V 0xc0006027
+#define MASK_VSSEG7E32V 0xfdf0707f
+#define MATCH_VLSEG8E32V 0xe0006007
+#define MASK_VLSEG8E32V 0xfdf0707f
+#define MATCH_VSSEG8E32V 0xe0006027
+#define MASK_VSSEG8E32V 0xfdf0707f
+#define MATCH_VLSEG2E64V 0x20007007
+#define MASK_VLSEG2E64V 0xfdf0707f
+#define MATCH_VSSEG2E64V 0x20007027
+#define MASK_VSSEG2E64V 0xfdf0707f
+#define MATCH_VLSEG3E64V 0x40007007
+#define MASK_VLSEG3E64V 0xfdf0707f
+#define MATCH_VSSEG3E64V 0x40007027
+#define MASK_VSSEG3E64V 0xfdf0707f
+#define MATCH_VLSEG4E64V 0x60007007
+#define MASK_VLSEG4E64V 0xfdf0707f
+#define MATCH_VSSEG4E64V 0x60007027
+#define MASK_VSSEG4E64V 0xfdf0707f
+#define MATCH_VLSEG5E64V 0x80007007
+#define MASK_VLSEG5E64V 0xfdf0707f
+#define MATCH_VSSEG5E64V 0x80007027
+#define MASK_VSSEG5E64V 0xfdf0707f
+#define MATCH_VLSEG6E64V 0xa0007007
+#define MASK_VLSEG6E64V 0xfdf0707f
+#define MATCH_VSSEG6E64V 0xa0007027
+#define MASK_VSSEG6E64V 0xfdf0707f
+#define MATCH_VLSEG7E64V 0xc0007007
+#define MASK_VLSEG7E64V 0xfdf0707f
+#define MATCH_VSSEG7E64V 0xc0007027
+#define MASK_VSSEG7E64V 0xfdf0707f
+#define MATCH_VLSEG8E64V 0xe0007007
+#define MASK_VLSEG8E64V 0xfdf0707f
+#define MATCH_VSSEG8E64V 0xe0007027
+#define MASK_VSSEG8E64V 0xfdf0707f
+#define MATCH_VLSSEG2E8V 0x28000007
+#define MASK_VLSSEG2E8V 0xfc00707f
+#define MATCH_VSSSEG2E8V 0x28000027
+#define MASK_VSSSEG2E8V 0xfc00707f
+#define MATCH_VLSSEG3E8V 0x48000007
+#define MASK_VLSSEG3E8V 0xfc00707f
+#define MATCH_VSSSEG3E8V 0x48000027
+#define MASK_VSSSEG3E8V 0xfc00707f
+#define MATCH_VLSSEG4E8V 0x68000007
+#define MASK_VLSSEG4E8V 0xfc00707f
+#define MATCH_VSSSEG4E8V 0x68000027
+#define MASK_VSSSEG4E8V 0xfc00707f
+#define MATCH_VLSSEG5E8V 0x88000007
+#define MASK_VLSSEG5E8V 0xfc00707f
+#define MATCH_VSSSEG5E8V 0x88000027
+#define MASK_VSSSEG5E8V 0xfc00707f
+#define MATCH_VLSSEG6E8V 0xa8000007
+#define MASK_VLSSEG6E8V 0xfc00707f
+#define MATCH_VSSSEG6E8V 0xa8000027
+#define MASK_VSSSEG6E8V 0xfc00707f
+#define MATCH_VLSSEG7E8V 0xc8000007
+#define MASK_VLSSEG7E8V 0xfc00707f
+#define MATCH_VSSSEG7E8V 0xc8000027
+#define MASK_VSSSEG7E8V 0xfc00707f
+#define MATCH_VLSSEG8E8V 0xe8000007
+#define MASK_VLSSEG8E8V 0xfc00707f
+#define MATCH_VSSSEG8E8V 0xe8000027
+#define MASK_VSSSEG8E8V 0xfc00707f
+#define MATCH_VLSSEG2E16V 0x28005007
+#define MASK_VLSSEG2E16V 0xfc00707f
+#define MATCH_VSSSEG2E16V 0x28005027
+#define MASK_VSSSEG2E16V 0xfc00707f
+#define MATCH_VLSSEG3E16V 0x48005007
+#define MASK_VLSSEG3E16V 0xfc00707f
+#define MATCH_VSSSEG3E16V 0x48005027
+#define MASK_VSSSEG3E16V 0xfc00707f
+#define MATCH_VLSSEG4E16V 0x68005007
+#define MASK_VLSSEG4E16V 0xfc00707f
+#define MATCH_VSSSEG4E16V 0x68005027
+#define MASK_VSSSEG4E16V 0xfc00707f
+#define MATCH_VLSSEG5E16V 0x88005007
+#define MASK_VLSSEG5E16V 0xfc00707f
+#define MATCH_VSSSEG5E16V 0x88005027
+#define MASK_VSSSEG5E16V 0xfc00707f
+#define MATCH_VLSSEG6E16V 0xa8005007
+#define MASK_VLSSEG6E16V 0xfc00707f
+#define MATCH_VSSSEG6E16V 0xa8005027
+#define MASK_VSSSEG6E16V 0xfc00707f
+#define MATCH_VLSSEG7E16V 0xc8005007
+#define MASK_VLSSEG7E16V 0xfc00707f
+#define MATCH_VSSSEG7E16V 0xc8005027
+#define MASK_VSSSEG7E16V 0xfc00707f
+#define MATCH_VLSSEG8E16V 0xe8005007
+#define MASK_VLSSEG8E16V 0xfc00707f
+#define MATCH_VSSSEG8E16V 0xe8005027
+#define MASK_VSSSEG8E16V 0xfc00707f
+#define MATCH_VLSSEG2E32V 0x28006007
+#define MASK_VLSSEG2E32V 0xfc00707f
+#define MATCH_VSSSEG2E32V 0x28006027
+#define MASK_VSSSEG2E32V 0xfc00707f
+#define MATCH_VLSSEG3E32V 0x48006007
+#define MASK_VLSSEG3E32V 0xfc00707f
+#define MATCH_VSSSEG3E32V 0x48006027
+#define MASK_VSSSEG3E32V 0xfc00707f
+#define MATCH_VLSSEG4E32V 0x68006007
+#define MASK_VLSSEG4E32V 0xfc00707f
+#define MATCH_VSSSEG4E32V 0x68006027
+#define MASK_VSSSEG4E32V 0xfc00707f
+#define MATCH_VLSSEG5E32V 0x88006007
+#define MASK_VLSSEG5E32V 0xfc00707f
+#define MATCH_VSSSEG5E32V 0x88006027
+#define MASK_VSSSEG5E32V 0xfc00707f
+#define MATCH_VLSSEG6E32V 0xa8006007
+#define MASK_VLSSEG6E32V 0xfc00707f
+#define MATCH_VSSSEG6E32V 0xa8006027
+#define MASK_VSSSEG6E32V 0xfc00707f
+#define MATCH_VLSSEG7E32V 0xc8006007
+#define MASK_VLSSEG7E32V 0xfc00707f
+#define MATCH_VSSSEG7E32V 0xc8006027
+#define MASK_VSSSEG7E32V 0xfc00707f
+#define MATCH_VLSSEG8E32V 0xe8006007
+#define MASK_VLSSEG8E32V 0xfc00707f
+#define MATCH_VSSSEG8E32V 0xe8006027
+#define MASK_VSSSEG8E32V 0xfc00707f
+#define MATCH_VLSSEG2E64V 0x28007007
+#define MASK_VLSSEG2E64V 0xfc00707f
+#define MATCH_VSSSEG2E64V 0x28007027
+#define MASK_VSSSEG2E64V 0xfc00707f
+#define MATCH_VLSSEG3E64V 0x48007007
+#define MASK_VLSSEG3E64V 0xfc00707f
+#define MATCH_VSSSEG3E64V 0x48007027
+#define MASK_VSSSEG3E64V 0xfc00707f
+#define MATCH_VLSSEG4E64V 0x68007007
+#define MASK_VLSSEG4E64V 0xfc00707f
+#define MATCH_VSSSEG4E64V 0x68007027
+#define MASK_VSSSEG4E64V 0xfc00707f
+#define MATCH_VLSSEG5E64V 0x88007007
+#define MASK_VLSSEG5E64V 0xfc00707f
+#define MATCH_VSSSEG5E64V 0x88007027
+#define MASK_VSSSEG5E64V 0xfc00707f
+#define MATCH_VLSSEG6E64V 0xa8007007
+#define MASK_VLSSEG6E64V 0xfc00707f
+#define MATCH_VSSSEG6E64V 0xa8007027
+#define MASK_VSSSEG6E64V 0xfc00707f
+#define MATCH_VLSSEG7E64V 0xc8007007
+#define MASK_VLSSEG7E64V 0xfc00707f
+#define MATCH_VSSSEG7E64V 0xc8007027
+#define MASK_VSSSEG7E64V 0xfc00707f
+#define MATCH_VLSSEG8E64V 0xe8007007
+#define MASK_VLSSEG8E64V 0xfc00707f
+#define MATCH_VSSSEG8E64V 0xe8007027
+#define MASK_VSSSEG8E64V 0xfc00707f
+#define MATCH_VLOXSEG2EI8V 0x2c000007
+#define MASK_VLOXSEG2EI8V 0xfc00707f
+#define MATCH_VSOXSEG2EI8V 0x2c000027
+#define MASK_VSOXSEG2EI8V 0xfc00707f
+#define MATCH_VLOXSEG3EI8V 0x4c000007
+#define MASK_VLOXSEG3EI8V 0xfc00707f
+#define MATCH_VSOXSEG3EI8V 0x4c000027
+#define MASK_VSOXSEG3EI8V 0xfc00707f
+#define MATCH_VLOXSEG4EI8V 0x6c000007
+#define MASK_VLOXSEG4EI8V 0xfc00707f
+#define MATCH_VSOXSEG4EI8V 0x6c000027
+#define MASK_VSOXSEG4EI8V 0xfc00707f
+#define MATCH_VLOXSEG5EI8V 0x8c000007
+#define MASK_VLOXSEG5EI8V 0xfc00707f
+#define MATCH_VSOXSEG5EI8V 0x8c000027
+#define MASK_VSOXSEG5EI8V 0xfc00707f
+#define MATCH_VLOXSEG6EI8V 0xac000007
+#define MASK_VLOXSEG6EI8V 0xfc00707f
+#define MATCH_VSOXSEG6EI8V 0xac000027
+#define MASK_VSOXSEG6EI8V 0xfc00707f
+#define MATCH_VLOXSEG7EI8V 0xcc000007
+#define MASK_VLOXSEG7EI8V 0xfc00707f
+#define MATCH_VSOXSEG7EI8V 0xcc000027
+#define MASK_VSOXSEG7EI8V 0xfc00707f
+#define MATCH_VLOXSEG8EI8V 0xec000007
+#define MASK_VLOXSEG8EI8V 0xfc00707f
+#define MATCH_VSOXSEG8EI8V 0xec000027
+#define MASK_VSOXSEG8EI8V 0xfc00707f
+#define MATCH_VLUXSEG2EI8V 0x24000007
+#define MASK_VLUXSEG2EI8V 0xfc00707f
+#define MATCH_VSUXSEG2EI8V 0x24000027
+#define MASK_VSUXSEG2EI8V 0xfc00707f
+#define MATCH_VLUXSEG3EI8V 0x44000007
+#define MASK_VLUXSEG3EI8V 0xfc00707f
+#define MATCH_VSUXSEG3EI8V 0x44000027
+#define MASK_VSUXSEG3EI8V 0xfc00707f
+#define MATCH_VLUXSEG4EI8V 0x64000007
+#define MASK_VLUXSEG4EI8V 0xfc00707f
+#define MATCH_VSUXSEG4EI8V 0x64000027
+#define MASK_VSUXSEG4EI8V 0xfc00707f
+#define MATCH_VLUXSEG5EI8V 0x84000007
+#define MASK_VLUXSEG5EI8V 0xfc00707f
+#define MATCH_VSUXSEG5EI8V 0x84000027
+#define MASK_VSUXSEG5EI8V 0xfc00707f
+#define MATCH_VLUXSEG6EI8V 0xa4000007
+#define MASK_VLUXSEG6EI8V 0xfc00707f
+#define MATCH_VSUXSEG6EI8V 0xa4000027
+#define MASK_VSUXSEG6EI8V 0xfc00707f
+#define MATCH_VLUXSEG7EI8V 0xc4000007
+#define MASK_VLUXSEG7EI8V 0xfc00707f
+#define MATCH_VSUXSEG7EI8V 0xc4000027
+#define MASK_VSUXSEG7EI8V 0xfc00707f
+#define MATCH_VLUXSEG8EI8V 0xe4000007
+#define MASK_VLUXSEG8EI8V 0xfc00707f
+#define MATCH_VSUXSEG8EI8V 0xe4000027
+#define MASK_VSUXSEG8EI8V 0xfc00707f
+#define MATCH_VLOXSEG2EI16V 0x2c005007
+#define MASK_VLOXSEG2EI16V 0xfc00707f
+#define MATCH_VSOXSEG2EI16V 0x2c005027
+#define MASK_VSOXSEG2EI16V 0xfc00707f
+#define MATCH_VLOXSEG3EI16V 0x4c005007
+#define MASK_VLOXSEG3EI16V 0xfc00707f
+#define MATCH_VSOXSEG3EI16V 0x4c005027
+#define MASK_VSOXSEG3EI16V 0xfc00707f
+#define MATCH_VLOXSEG4EI16V 0x6c005007
+#define MASK_VLOXSEG4EI16V 0xfc00707f
+#define MATCH_VSOXSEG4EI16V 0x6c005027
+#define MASK_VSOXSEG4EI16V 0xfc00707f
+#define MATCH_VLOXSEG5EI16V 0x8c005007
+#define MASK_VLOXSEG5EI16V 0xfc00707f
+#define MATCH_VSOXSEG5EI16V 0x8c005027
+#define MASK_VSOXSEG5EI16V 0xfc00707f
+#define MATCH_VLOXSEG6EI16V 0xac005007
+#define MASK_VLOXSEG6EI16V 0xfc00707f
+#define MATCH_VSOXSEG6EI16V 0xac005027
+#define MASK_VSOXSEG6EI16V 0xfc00707f
+#define MATCH_VLOXSEG7EI16V 0xcc005007
+#define MASK_VLOXSEG7EI16V 0xfc00707f
+#define MATCH_VSOXSEG7EI16V 0xcc005027
+#define MASK_VSOXSEG7EI16V 0xfc00707f
+#define MATCH_VLOXSEG8EI16V 0xec005007
+#define MASK_VLOXSEG8EI16V 0xfc00707f
+#define MATCH_VSOXSEG8EI16V 0xec005027
+#define MASK_VSOXSEG8EI16V 0xfc00707f
+#define MATCH_VLUXSEG2EI16V 0x24005007
+#define MASK_VLUXSEG2EI16V 0xfc00707f
+#define MATCH_VSUXSEG2EI16V 0x24005027
+#define MASK_VSUXSEG2EI16V 0xfc00707f
+#define MATCH_VLUXSEG3EI16V 0x44005007
+#define MASK_VLUXSEG3EI16V 0xfc00707f
+#define MATCH_VSUXSEG3EI16V 0x44005027
+#define MASK_VSUXSEG3EI16V 0xfc00707f
+#define MATCH_VLUXSEG4EI16V 0x64005007
+#define MASK_VLUXSEG4EI16V 0xfc00707f
+#define MATCH_VSUXSEG4EI16V 0x64005027
+#define MASK_VSUXSEG4EI16V 0xfc00707f
+#define MATCH_VLUXSEG5EI16V 0x84005007
+#define MASK_VLUXSEG5EI16V 0xfc00707f
+#define MATCH_VSUXSEG5EI16V 0x84005027
+#define MASK_VSUXSEG5EI16V 0xfc00707f
+#define MATCH_VLUXSEG6EI16V 0xa4005007
+#define MASK_VLUXSEG6EI16V 0xfc00707f
+#define MATCH_VSUXSEG6EI16V 0xa4005027
+#define MASK_VSUXSEG6EI16V 0xfc00707f
+#define MATCH_VLUXSEG7EI16V 0xc4005007
+#define MASK_VLUXSEG7EI16V 0xfc00707f
+#define MATCH_VSUXSEG7EI16V 0xc4005027
+#define MASK_VSUXSEG7EI16V 0xfc00707f
+#define MATCH_VLUXSEG8EI16V 0xe4005007
+#define MASK_VLUXSEG8EI16V 0xfc00707f
+#define MATCH_VSUXSEG8EI16V 0xe4005027
+#define MASK_VSUXSEG8EI16V 0xfc00707f
+#define MATCH_VLOXSEG2EI32V 0x2c006007
+#define MASK_VLOXSEG2EI32V 0xfc00707f
+#define MATCH_VSOXSEG2EI32V 0x2c006027
+#define MASK_VSOXSEG2EI32V 0xfc00707f
+#define MATCH_VLOXSEG3EI32V 0x4c006007
+#define MASK_VLOXSEG3EI32V 0xfc00707f
+#define MATCH_VSOXSEG3EI32V 0x4c006027
+#define MASK_VSOXSEG3EI32V 0xfc00707f
+#define MATCH_VLOXSEG4EI32V 0x6c006007
+#define MASK_VLOXSEG4EI32V 0xfc00707f
+#define MATCH_VSOXSEG4EI32V 0x6c006027
+#define MASK_VSOXSEG4EI32V 0xfc00707f
+#define MATCH_VLOXSEG5EI32V 0x8c006007
+#define MASK_VLOXSEG5EI32V 0xfc00707f
+#define MATCH_VSOXSEG5EI32V 0x8c006027
+#define MASK_VSOXSEG5EI32V 0xfc00707f
+#define MATCH_VLOXSEG6EI32V 0xac006007
+#define MASK_VLOXSEG6EI32V 0xfc00707f
+#define MATCH_VSOXSEG6EI32V 0xac006027
+#define MASK_VSOXSEG6EI32V 0xfc00707f
+#define MATCH_VLOXSEG7EI32V 0xcc006007
+#define MASK_VLOXSEG7EI32V 0xfc00707f
+#define MATCH_VSOXSEG7EI32V 0xcc006027
+#define MASK_VSOXSEG7EI32V 0xfc00707f
+#define MATCH_VLOXSEG8EI32V 0xec006007
+#define MASK_VLOXSEG8EI32V 0xfc00707f
+#define MATCH_VSOXSEG8EI32V 0xec006027
+#define MASK_VSOXSEG8EI32V 0xfc00707f
+#define MATCH_VLUXSEG2EI32V 0x24006007
+#define MASK_VLUXSEG2EI32V 0xfc00707f
+#define MATCH_VSUXSEG2EI32V 0x24006027
+#define MASK_VSUXSEG2EI32V 0xfc00707f
+#define MATCH_VLUXSEG3EI32V 0x44006007
+#define MASK_VLUXSEG3EI32V 0xfc00707f
+#define MATCH_VSUXSEG3EI32V 0x44006027
+#define MASK_VSUXSEG3EI32V 0xfc00707f
+#define MATCH_VLUXSEG4EI32V 0x64006007
+#define MASK_VLUXSEG4EI32V 0xfc00707f
+#define MATCH_VSUXSEG4EI32V 0x64006027
+#define MASK_VSUXSEG4EI32V 0xfc00707f
+#define MATCH_VLUXSEG5EI32V 0x84006007
+#define MASK_VLUXSEG5EI32V 0xfc00707f
+#define MATCH_VSUXSEG5EI32V 0x84006027
+#define MASK_VSUXSEG5EI32V 0xfc00707f
+#define MATCH_VLUXSEG6EI32V 0xa4006007
+#define MASK_VLUXSEG6EI32V 0xfc00707f
+#define MATCH_VSUXSEG6EI32V 0xa4006027
+#define MASK_VSUXSEG6EI32V 0xfc00707f
+#define MATCH_VLUXSEG7EI32V 0xc4006007
+#define MASK_VLUXSEG7EI32V 0xfc00707f
+#define MATCH_VSUXSEG7EI32V 0xc4006027
+#define MASK_VSUXSEG7EI32V 0xfc00707f
+#define MATCH_VLUXSEG8EI32V 0xe4006007
+#define MASK_VLUXSEG8EI32V 0xfc00707f
+#define MATCH_VSUXSEG8EI32V 0xe4006027
+#define MASK_VSUXSEG8EI32V 0xfc00707f
+#define MATCH_VLOXSEG2EI64V 0x2c007007
+#define MASK_VLOXSEG2EI64V 0xfc00707f
+#define MATCH_VSOXSEG2EI64V 0x2c007027
+#define MASK_VSOXSEG2EI64V 0xfc00707f
+#define MATCH_VLOXSEG3EI64V 0x4c007007
+#define MASK_VLOXSEG3EI64V 0xfc00707f
+#define MATCH_VSOXSEG3EI64V 0x4c007027
+#define MASK_VSOXSEG3EI64V 0xfc00707f
+#define MATCH_VLOXSEG4EI64V 0x6c007007
+#define MASK_VLOXSEG4EI64V 0xfc00707f
+#define MATCH_VSOXSEG4EI64V 0x6c007027
+#define MASK_VSOXSEG4EI64V 0xfc00707f
+#define MATCH_VLOXSEG5EI64V 0x8c007007
+#define MASK_VLOXSEG5EI64V 0xfc00707f
+#define MATCH_VSOXSEG5EI64V 0x8c007027
+#define MASK_VSOXSEG5EI64V 0xfc00707f
+#define MATCH_VLOXSEG6EI64V 0xac007007
+#define MASK_VLOXSEG6EI64V 0xfc00707f
+#define MATCH_VSOXSEG6EI64V 0xac007027
+#define MASK_VSOXSEG6EI64V 0xfc00707f
+#define MATCH_VLOXSEG7EI64V 0xcc007007
+#define MASK_VLOXSEG7EI64V 0xfc00707f
+#define MATCH_VSOXSEG7EI64V 0xcc007027
+#define MASK_VSOXSEG7EI64V 0xfc00707f
+#define MATCH_VLOXSEG8EI64V 0xec007007
+#define MASK_VLOXSEG8EI64V 0xfc00707f
+#define MATCH_VSOXSEG8EI64V 0xec007027
+#define MASK_VSOXSEG8EI64V 0xfc00707f
+#define MATCH_VLUXSEG2EI64V 0x24007007
+#define MASK_VLUXSEG2EI64V 0xfc00707f
+#define MATCH_VSUXSEG2EI64V 0x24007027
+#define MASK_VSUXSEG2EI64V 0xfc00707f
+#define MATCH_VLUXSEG3EI64V 0x44007007
+#define MASK_VLUXSEG3EI64V 0xfc00707f
+#define MATCH_VSUXSEG3EI64V 0x44007027
+#define MASK_VSUXSEG3EI64V 0xfc00707f
+#define MATCH_VLUXSEG4EI64V 0x64007007
+#define MASK_VLUXSEG4EI64V 0xfc00707f
+#define MATCH_VSUXSEG4EI64V 0x64007027
+#define MASK_VSUXSEG4EI64V 0xfc00707f
+#define MATCH_VLUXSEG5EI64V 0x84007007
+#define MASK_VLUXSEG5EI64V 0xfc00707f
+#define MATCH_VSUXSEG5EI64V 0x84007027
+#define MASK_VSUXSEG5EI64V 0xfc00707f
+#define MATCH_VLUXSEG6EI64V 0xa4007007
+#define MASK_VLUXSEG6EI64V 0xfc00707f
+#define MATCH_VSUXSEG6EI64V 0xa4007027
+#define MASK_VSUXSEG6EI64V 0xfc00707f
+#define MATCH_VLUXSEG7EI64V 0xc4007007
+#define MASK_VLUXSEG7EI64V 0xfc00707f
+#define MATCH_VSUXSEG7EI64V 0xc4007027
+#define MASK_VSUXSEG7EI64V 0xfc00707f
+#define MATCH_VLUXSEG8EI64V 0xe4007007
+#define MASK_VLUXSEG8EI64V 0xfc00707f
+#define MATCH_VSUXSEG8EI64V 0xe4007027
+#define MASK_VSUXSEG8EI64V 0xfc00707f
+#define MATCH_VLSEG2E8FFV 0x21000007
+#define MASK_VLSEG2E8FFV 0xfdf0707f
+#define MATCH_VLSEG3E8FFV 0x41000007
+#define MASK_VLSEG3E8FFV 0xfdf0707f
+#define MATCH_VLSEG4E8FFV 0x61000007
+#define MASK_VLSEG4E8FFV 0xfdf0707f
+#define MATCH_VLSEG5E8FFV 0x81000007
+#define MASK_VLSEG5E8FFV 0xfdf0707f
+#define MATCH_VLSEG6E8FFV 0xa1000007
+#define MASK_VLSEG6E8FFV 0xfdf0707f
+#define MATCH_VLSEG7E8FFV 0xc1000007
+#define MASK_VLSEG7E8FFV 0xfdf0707f
+#define MATCH_VLSEG8E8FFV 0xe1000007
+#define MASK_VLSEG8E8FFV 0xfdf0707f
+#define MATCH_VLSEG2E16FFV 0x21005007
+#define MASK_VLSEG2E16FFV 0xfdf0707f
+#define MATCH_VLSEG3E16FFV 0x41005007
+#define MASK_VLSEG3E16FFV 0xfdf0707f
+#define MATCH_VLSEG4E16FFV 0x61005007
+#define MASK_VLSEG4E16FFV 0xfdf0707f
+#define MATCH_VLSEG5E16FFV 0x81005007
+#define MASK_VLSEG5E16FFV 0xfdf0707f
+#define MATCH_VLSEG6E16FFV 0xa1005007
+#define MASK_VLSEG6E16FFV 0xfdf0707f
+#define MATCH_VLSEG7E16FFV 0xc1005007
+#define MASK_VLSEG7E16FFV 0xfdf0707f
+#define MATCH_VLSEG8E16FFV 0xe1005007
+#define MASK_VLSEG8E16FFV 0xfdf0707f
+#define MATCH_VLSEG2E32FFV 0x21006007
+#define MASK_VLSEG2E32FFV 0xfdf0707f
+#define MATCH_VLSEG3E32FFV 0x41006007
+#define MASK_VLSEG3E32FFV 0xfdf0707f
+#define MATCH_VLSEG4E32FFV 0x61006007
+#define MASK_VLSEG4E32FFV 0xfdf0707f
+#define MATCH_VLSEG5E32FFV 0x81006007
+#define MASK_VLSEG5E32FFV 0xfdf0707f
+#define MATCH_VLSEG6E32FFV 0xa1006007
+#define MASK_VLSEG6E32FFV 0xfdf0707f
+#define MATCH_VLSEG7E32FFV 0xc1006007
+#define MASK_VLSEG7E32FFV 0xfdf0707f
+#define MATCH_VLSEG8E32FFV 0xe1006007
+#define MASK_VLSEG8E32FFV 0xfdf0707f
+#define MATCH_VLSEG2E64FFV 0x21007007
+#define MASK_VLSEG2E64FFV 0xfdf0707f
+#define MATCH_VLSEG3E64FFV 0x41007007
+#define MASK_VLSEG3E64FFV 0xfdf0707f
+#define MATCH_VLSEG4E64FFV 0x61007007
+#define MASK_VLSEG4E64FFV 0xfdf0707f
+#define MATCH_VLSEG5E64FFV 0x81007007
+#define MASK_VLSEG5E64FFV 0xfdf0707f
+#define MATCH_VLSEG6E64FFV 0xa1007007
+#define MASK_VLSEG6E64FFV 0xfdf0707f
+#define MATCH_VLSEG7E64FFV 0xc1007007
+#define MASK_VLSEG7E64FFV 0xfdf0707f
+#define MATCH_VLSEG8E64FFV 0xe1007007
+#define MASK_VLSEG8E64FFV 0xfdf0707f
+#define MATCH_VL1RE8V 0x02800007
+#define MASK_VL1RE8V 0xfff0707f
+#define MATCH_VL1RE16V 0x02805007
+#define MASK_VL1RE16V 0xfff0707f
+#define MATCH_VL1RE32V 0x02806007
+#define MASK_VL1RE32V 0xfff0707f
+#define MATCH_VL1RE64V 0x02807007
+#define MASK_VL1RE64V 0xfff0707f
+#define MATCH_VL2RE8V 0x22800007
+#define MASK_VL2RE8V 0xfff0707f
+#define MATCH_VL2RE16V 0x22805007
+#define MASK_VL2RE16V 0xfff0707f
+#define MATCH_VL2RE32V 0x22806007
+#define MASK_VL2RE32V 0xfff0707f
+#define MATCH_VL2RE64V 0x22807007
+#define MASK_VL2RE64V 0xfff0707f
+#define MATCH_VL4RE8V 0x62800007
+#define MASK_VL4RE8V 0xfff0707f
+#define MATCH_VL4RE16V 0x62805007
+#define MASK_VL4RE16V 0xfff0707f
+#define MATCH_VL4RE32V 0x62806007
+#define MASK_VL4RE32V 0xfff0707f
+#define MATCH_VL4RE64V 0x62807007
+#define MASK_VL4RE64V 0xfff0707f
+#define MATCH_VL8RE8V 0xe2800007
+#define MASK_VL8RE8V 0xfff0707f
+#define MATCH_VL8RE16V 0xe2805007
+#define MASK_VL8RE16V 0xfff0707f
+#define MATCH_VL8RE32V 0xe2806007
+#define MASK_VL8RE32V 0xfff0707f
+#define MATCH_VL8RE64V 0xe2807007
+#define MASK_VL8RE64V 0xfff0707f
+#define MATCH_VS1RV 0x02800027
+#define MASK_VS1RV 0xfff0707f
+#define MATCH_VS2RV 0x22800027
+#define MASK_VS2RV 0xfff0707f
+#define MATCH_VS4RV 0x62800027
+#define MASK_VS4RV 0xfff0707f
+#define MATCH_VS8RV 0xe2800027
+#define MASK_VS8RV 0xfff0707f
+#define MATCH_VADDVV 0x00000057
+#define MASK_VADDVV 0xfc00707f
+#define MATCH_VADDVX 0x00004057
+#define MASK_VADDVX 0xfc00707f
+#define MATCH_VADDVI 0x00003057
+#define MASK_VADDVI 0xfc00707f
+#define MATCH_VSUBVV 0x08000057
+#define MASK_VSUBVV 0xfc00707f
+#define MATCH_VSUBVX 0x08004057
+#define MASK_VSUBVX 0xfc00707f
+#define MATCH_VRSUBVX 0x0c004057
+#define MASK_VRSUBVX 0xfc00707f
+#define MATCH_VRSUBVI 0x0c003057
+#define MASK_VRSUBVI 0xfc00707f
+#define MATCH_VWCVTXXV 0xc4006057
+#define MASK_VWCVTXXV 0xfc0ff07f
+#define MATCH_VWCVTUXXV 0xc0006057
+#define MASK_VWCVTUXXV 0xfc0ff07f
+#define MATCH_VWADDVV 0xc4002057
+#define MASK_VWADDVV 0xfc00707f
+#define MATCH_VWADDVX 0xc4006057
+#define MASK_VWADDVX 0xfc00707f
+#define MATCH_VWSUBVV 0xcc002057
+#define MASK_VWSUBVV 0xfc00707f
+#define MATCH_VWSUBVX 0xcc006057
+#define MASK_VWSUBVX 0xfc00707f
+#define MATCH_VWADDWV 0xd4002057
+#define MASK_VWADDWV 0xfc00707f
+#define MATCH_VWADDWX 0xd4006057
+#define MASK_VWADDWX 0xfc00707f
+#define MATCH_VWSUBWV 0xdc002057
+#define MASK_VWSUBWV 0xfc00707f
+#define MATCH_VWSUBWX 0xdc006057
+#define MASK_VWSUBWX 0xfc00707f
+#define MATCH_VWADDUVV 0xc0002057
+#define MASK_VWADDUVV 0xfc00707f
+#define MATCH_VWADDUVX 0xc0006057
+#define MASK_VWADDUVX 0xfc00707f
+#define MATCH_VWSUBUVV 0xc8002057
+#define MASK_VWSUBUVV 0xfc00707f
+#define MATCH_VWSUBUVX 0xc8006057
+#define MASK_VWSUBUVX 0xfc00707f
+#define MATCH_VWADDUWV 0xd0002057
+#define MASK_VWADDUWV 0xfc00707f
+#define MATCH_VWADDUWX 0xd0006057
+#define MASK_VWADDUWX 0xfc00707f
+#define MATCH_VWSUBUWV 0xd8002057
+#define MASK_VWSUBUWV 0xfc00707f
+#define MATCH_VWSUBUWX 0xd8006057
+#define MASK_VWSUBUWX 0xfc00707f
+#define MATCH_VZEXT_VF8 0x48012057
+#define MASK_VZEXT_VF8 0xfc0ff07f
+#define MATCH_VSEXT_VF8 0x4801a057
+#define MASK_VSEXT_VF8 0xfc0ff07f
+#define MATCH_VZEXT_VF4 0x48022057
+#define MASK_VZEXT_VF4 0xfc0ff07f
+#define MATCH_VSEXT_VF4 0x4802a057
+#define MASK_VSEXT_VF4 0xfc0ff07f
+#define MATCH_VZEXT_VF2 0x48032057
+#define MASK_VZEXT_VF2 0xfc0ff07f
+#define MATCH_VSEXT_VF2 0x4803a057
+#define MASK_VSEXT_VF2 0xfc0ff07f
+#define MATCH_VADCVVM 0x40000057
+#define MASK_VADCVVM 0xfe00707f
+#define MATCH_VADCVXM 0x40004057
+#define MASK_VADCVXM 0xfe00707f
+#define MATCH_VADCVIM 0x40003057
+#define MASK_VADCVIM 0xfe00707f
+#define MATCH_VMADCVVM 0x44000057
+#define MASK_VMADCVVM 0xfe00707f
+#define MATCH_VMADCVXM 0x44004057
+#define MASK_VMADCVXM 0xfe00707f
+#define MATCH_VMADCVIM 0x44003057
+#define MASK_VMADCVIM 0xfe00707f
+#define MATCH_VMADCVV 0x46000057
+#define MASK_VMADCVV 0xfe00707f
+#define MATCH_VMADCVX 0x46004057
+#define MASK_VMADCVX 0xfe00707f
+#define MATCH_VMADCVI 0x46003057
+#define MASK_VMADCVI 0xfe00707f
+#define MATCH_VSBCVVM 0x48000057
+#define MASK_VSBCVVM 0xfe00707f
+#define MATCH_VSBCVXM 0x48004057
+#define MASK_VSBCVXM 0xfe00707f
+#define MATCH_VMSBCVVM 0x4c000057
+#define MASK_VMSBCVVM 0xfe00707f
+#define MATCH_VMSBCVXM 0x4c004057
+#define MASK_VMSBCVXM 0xfe00707f
+#define MATCH_VMSBCVV 0x4e000057
+#define MASK_VMSBCVV 0xfe00707f
+#define MATCH_VMSBCVX 0x4e004057
+#define MASK_VMSBCVX 0xfe00707f
+#define MATCH_VNOTV 0x2c0fb057
+#define MASK_VNOTV 0xfc0ff07f
+#define MATCH_VANDVV 0x24000057
+#define MASK_VANDVV 0xfc00707f
+#define MATCH_VANDVX 0x24004057
+#define MASK_VANDVX 0xfc00707f
+#define MATCH_VANDVI 0x24003057
+#define MASK_VANDVI 0xfc00707f
+#define MATCH_VORVV 0x28000057
+#define MASK_VORVV 0xfc00707f
+#define MATCH_VORVX 0x28004057
+#define MASK_VORVX 0xfc00707f
+#define MATCH_VORVI 0x28003057
+#define MASK_VORVI 0xfc00707f
+#define MATCH_VXORVV 0x2c000057
+#define MASK_VXORVV 0xfc00707f
+#define MATCH_VXORVX 0x2c004057
+#define MASK_VXORVX 0xfc00707f
+#define MATCH_VXORVI 0x2c003057
+#define MASK_VXORVI 0xfc00707f
+#define MATCH_VSLLVV 0x94000057
+#define MASK_VSLLVV 0xfc00707f
+#define MATCH_VSLLVX 0x94004057
+#define MASK_VSLLVX 0xfc00707f
+#define MATCH_VSLLVI 0x94003057
+#define MASK_VSLLVI 0xfc00707f
+#define MATCH_VSRLVV 0xa0000057
+#define MASK_VSRLVV 0xfc00707f
+#define MATCH_VSRLVX 0xa0004057
+#define MASK_VSRLVX 0xfc00707f
+#define MATCH_VSRLVI 0xa0003057
+#define MASK_VSRLVI 0xfc00707f
+#define MATCH_VSRAVV 0xa4000057
+#define MASK_VSRAVV 0xfc00707f
+#define MATCH_VSRAVX 0xa4004057
+#define MASK_VSRAVX 0xfc00707f
+#define MATCH_VSRAVI 0xa4003057
+#define MASK_VSRAVI 0xfc00707f
+#define MATCH_VNCVTXXW 0xb0004057
+#define MASK_VNCVTXXW 0xfc0ff07f
+#define MATCH_VNSRLWV 0xb0000057
+#define MASK_VNSRLWV 0xfc00707f
+#define MATCH_VNSRLWX 0xb0004057
+#define MASK_VNSRLWX 0xfc00707f
+#define MATCH_VNSRLWI 0xb0003057
+#define MASK_VNSRLWI 0xfc00707f
+#define MATCH_VNSRAWV 0xb4000057
+#define MASK_VNSRAWV 0xfc00707f
+#define MATCH_VNSRAWX 0xb4004057
+#define MASK_VNSRAWX 0xfc00707f
+#define MATCH_VNSRAWI 0xb4003057
+#define MASK_VNSRAWI 0xfc00707f
+#define MATCH_VMSEQVV 0x60000057
+#define MASK_VMSEQVV 0xfc00707f
+#define MATCH_VMSEQVX 0x60004057
+#define MASK_VMSEQVX 0xfc00707f
+#define MATCH_VMSEQVI 0x60003057
+#define MASK_VMSEQVI 0xfc00707f
+#define MATCH_VMSNEVV 0x64000057
+#define MASK_VMSNEVV 0xfc00707f
+#define MATCH_VMSNEVX 0x64004057
+#define MASK_VMSNEVX 0xfc00707f
+#define MATCH_VMSNEVI 0x64003057
+#define MASK_VMSNEVI 0xfc00707f
+#define MATCH_VMSLTVV 0x6c000057
+#define MASK_VMSLTVV 0xfc00707f
+#define MATCH_VMSLTVX 0x6c004057
+#define MASK_VMSLTVX 0xfc00707f
+#define MATCH_VMSLTUVV 0x68000057
+#define MASK_VMSLTUVV 0xfc00707f
+#define MATCH_VMSLTUVX 0x68004057
+#define MASK_VMSLTUVX 0xfc00707f
+#define MATCH_VMSLEVV 0x74000057
+#define MASK_VMSLEVV 0xfc00707f
+#define MATCH_VMSLEVX 0x74004057
+#define MASK_VMSLEVX 0xfc00707f
+#define MATCH_VMSLEVI 0x74003057
+#define MASK_VMSLEVI 0xfc00707f
+#define MATCH_VMSLEUVV 0x70000057
+#define MASK_VMSLEUVV 0xfc00707f
+#define MATCH_VMSLEUVX 0x70004057
+#define MASK_VMSLEUVX 0xfc00707f
+#define MATCH_VMSLEUVI 0x70003057
+#define MASK_VMSLEUVI 0xfc00707f
+#define MATCH_VMSGTVX 0x7c004057
+#define MASK_VMSGTVX 0xfc00707f
+#define MATCH_VMSGTVI 0x7c003057
+#define MASK_VMSGTVI 0xfc00707f
+#define MATCH_VMSGTUVX 0x78004057
+#define MASK_VMSGTUVX 0xfc00707f
+#define MATCH_VMSGTUVI 0x78003057
+#define MASK_VMSGTUVI 0xfc00707f
+#define MATCH_VMINVV 0x14000057
+#define MASK_VMINVV 0xfc00707f
+#define MATCH_VMINVX 0x14004057
+#define MASK_VMINVX 0xfc00707f
+#define MATCH_VMAXVV 0x1c000057
+#define MASK_VMAXVV 0xfc00707f
+#define MATCH_VMAXVX 0x1c004057
+#define MASK_VMAXVX 0xfc00707f
+#define MATCH_VMINUVV 0x10000057
+#define MASK_VMINUVV 0xfc00707f
+#define MATCH_VMINUVX 0x10004057
+#define MASK_VMINUVX 0xfc00707f
+#define MATCH_VMAXUVV 0x18000057
+#define MASK_VMAXUVV 0xfc00707f
+#define MATCH_VMAXUVX 0x18004057
+#define MASK_VMAXUVX 0xfc00707f
+#define MATCH_VMULVV 0x94002057
+#define MASK_VMULVV 0xfc00707f
+#define MATCH_VMULVX 0x94006057
+#define MASK_VMULVX 0xfc00707f
+#define MATCH_VMULHVV 0x9c002057
+#define MASK_VMULHVV 0xfc00707f
+#define MATCH_VMULHVX 0x9c006057
+#define MASK_VMULHVX 0xfc00707f
+#define MATCH_VMULHUVV 0x90002057
+#define MASK_VMULHUVV 0xfc00707f
+#define MATCH_VMULHUVX 0x90006057
+#define MASK_VMULHUVX 0xfc00707f
+#define MATCH_VMULHSUVV 0x98002057
+#define MASK_VMULHSUVV 0xfc00707f
+#define MATCH_VMULHSUVX 0x98006057
+#define MASK_VMULHSUVX 0xfc00707f
+#define MATCH_VWMULVV 0xec002057
+#define MASK_VWMULVV 0xfc00707f
+#define MATCH_VWMULVX 0xec006057
+#define MASK_VWMULVX 0xfc00707f
+#define MATCH_VWMULUVV 0xe0002057
+#define MASK_VWMULUVV 0xfc00707f
+#define MATCH_VWMULUVX 0xe0006057
+#define MASK_VWMULUVX 0xfc00707f
+#define MATCH_VWMULSUVV 0xe8002057
+#define MASK_VWMULSUVV 0xfc00707f
+#define MATCH_VWMULSUVX 0xe8006057
+#define MASK_VWMULSUVX 0xfc00707f
+#define MATCH_VMACCVV 0xb4002057
+#define MASK_VMACCVV 0xfc00707f
+#define MATCH_VMACCVX 0xb4006057
+#define MASK_VMACCVX 0xfc00707f
+#define MATCH_VNMSACVV 0xbc002057
+#define MASK_VNMSACVV 0xfc00707f
+#define MATCH_VNMSACVX 0xbc006057
+#define MASK_VNMSACVX 0xfc00707f
+#define MATCH_VMADDVV 0xa4002057
+#define MASK_VMADDVV 0xfc00707f
+#define MATCH_VMADDVX 0xa4006057
+#define MASK_VMADDVX 0xfc00707f
+#define MATCH_VNMSUBVV 0xac002057
+#define MASK_VNMSUBVV 0xfc00707f
+#define MATCH_VNMSUBVX 0xac006057
+#define MASK_VNMSUBVX 0xfc00707f
+#define MATCH_VWMACCUVV 0xf0002057
+#define MASK_VWMACCUVV 0xfc00707f
+#define MATCH_VWMACCUVX 0xf0006057
+#define MASK_VWMACCUVX 0xfc00707f
+#define MATCH_VWMACCVV 0xf4002057
+#define MASK_VWMACCVV 0xfc00707f
+#define MATCH_VWMACCVX 0xf4006057
+#define MASK_VWMACCVX 0xfc00707f
+#define MATCH_VWMACCSUVV 0xfc002057
+#define MASK_VWMACCSUVV 0xfc00707f
+#define MATCH_VWMACCSUVX 0xfc006057
+#define MASK_VWMACCSUVX 0xfc00707f
+#define MATCH_VWMACCUSVX 0xf8006057
+#define MASK_VWMACCUSVX 0xfc00707f
+#define MATCH_VQMACCUVV 0xf0000057
+#define MASK_VQMACCUVV 0xfc00707f
+#define MATCH_VQMACCUVX 0xf0004057
+#define MASK_VQMACCUVX 0xfc00707f
+#define MATCH_VQMACCVV 0xf4000057
+#define MASK_VQMACCVV 0xfc00707f
+#define MATCH_VQMACCVX 0xf4004057
+#define MASK_VQMACCVX 0xfc00707f
+#define MATCH_VQMACCSUVV 0xfc000057
+#define MASK_VQMACCSUVV 0xfc00707f
+#define MATCH_VQMACCSUVX 0xfc004057
+#define MASK_VQMACCSUVX 0xfc00707f
+#define MATCH_VQMACCUSVX 0xf8004057
+#define MASK_VQMACCUSVX 0xfc00707f
+#define MATCH_VDIVVV 0x84002057
+#define MASK_VDIVVV 0xfc00707f
+#define MATCH_VDIVVX 0x84006057
+#define MASK_VDIVVX 0xfc00707f
+#define MATCH_VDIVUVV 0x80002057
+#define MASK_VDIVUVV 0xfc00707f
+#define MATCH_VDIVUVX 0x80006057
+#define MASK_VDIVUVX 0xfc00707f
+#define MATCH_VREMVV 0x8c002057
+#define MASK_VREMVV 0xfc00707f
+#define MATCH_VREMVX 0x8c006057
+#define MASK_VREMVX 0xfc00707f
+#define MATCH_VREMUVV 0x88002057
+#define MASK_VREMUVV 0xfc00707f
+#define MATCH_VREMUVX 0x88006057
+#define MASK_VREMUVX 0xfc00707f
+#define MATCH_VMERGEVVM 0x5c000057
+#define MASK_VMERGEVVM 0xfe00707f
+#define MATCH_VMERGEVXM 0x5c004057
+#define MASK_VMERGEVXM 0xfe00707f
+#define MATCH_VMERGEVIM 0x5c003057
+#define MASK_VMERGEVIM 0xfe00707f
+#define MATCH_VMVVV 0x5e000057
+#define MASK_VMVVV 0xfff0707f
+#define MATCH_VMVVX 0x5e004057
+#define MASK_VMVVX 0xfff0707f
+#define MATCH_VMVVI 0x5e003057
+#define MASK_VMVVI 0xfff0707f
+#define MATCH_VSADDUVV 0x80000057
+#define MASK_VSADDUVV 0xfc00707f
+#define MATCH_VSADDUVX 0x80004057
+#define MASK_VSADDUVX 0xfc00707f
+#define MATCH_VSADDUVI 0x80003057
+#define MASK_VSADDUVI 0xfc00707f
+#define MATCH_VSADDVV 0x84000057
+#define MASK_VSADDVV 0xfc00707f
+#define MATCH_VSADDVX 0x84004057
+#define MASK_VSADDVX 0xfc00707f
+#define MATCH_VSADDVI 0x84003057
+#define MASK_VSADDVI 0xfc00707f
+#define MATCH_VSSUBUVV 0x88000057
+#define MASK_VSSUBUVV 0xfc00707f
+#define MATCH_VSSUBUVX 0x88004057
+#define MASK_VSSUBUVX 0xfc00707f
+#define MATCH_VSSUBVV 0x8c000057
+#define MASK_VSSUBVV 0xfc00707f
+#define MATCH_VSSUBVX 0x8c004057
+#define MASK_VSSUBVX 0xfc00707f
+#define MATCH_VAADDUVV 0x20002057
+#define MASK_VAADDUVV 0xfc00707f
+#define MATCH_VAADDUVX 0x20006057
+#define MASK_VAADDUVX 0xfc00707f
+#define MATCH_VAADDVV 0x24002057
+#define MASK_VAADDVV 0xfc00707f
+#define MATCH_VAADDVX 0x24006057
+#define MASK_VAADDVX 0xfc00707f
+#define MATCH_VASUBUVV 0x28002057
+#define MASK_VASUBUVV 0xfc00707f
+#define MATCH_VASUBUVX 0x28006057
+#define MASK_VASUBUVX 0xfc00707f
+#define MATCH_VASUBVV 0x2c002057
+#define MASK_VASUBVV 0xfc00707f
+#define MATCH_VASUBVX 0x2c006057
+#define MASK_VASUBVX 0xfc00707f
+#define MATCH_VSMULVV 0x9c000057
+#define MASK_VSMULVV 0xfc00707f
+#define MATCH_VSMULVX 0x9c004057
+#define MASK_VSMULVX 0xfc00707f
+#define MATCH_VSSRLVV 0xa8000057
+#define MASK_VSSRLVV 0xfc00707f
+#define MATCH_VSSRLVX 0xa8004057
+#define MASK_VSSRLVX 0xfc00707f
+#define MATCH_VSSRLVI 0xa8003057
+#define MASK_VSSRLVI 0xfc00707f
+#define MATCH_VSSRAVV 0xac000057
+#define MASK_VSSRAVV 0xfc00707f
+#define MATCH_VSSRAVX 0xac004057
+#define MASK_VSSRAVX 0xfc00707f
+#define MATCH_VSSRAVI 0xac003057
+#define MASK_VSSRAVI 0xfc00707f
+#define MATCH_VNCLIPUWV 0xb8000057
+#define MASK_VNCLIPUWV 0xfc00707f
+#define MATCH_VNCLIPUWX 0xb8004057
+#define MASK_VNCLIPUWX 0xfc00707f
+#define MATCH_VNCLIPUWI 0xb8003057
+#define MASK_VNCLIPUWI 0xfc00707f
+#define MATCH_VNCLIPWV 0xbc000057
+#define MASK_VNCLIPWV 0xfc00707f
+#define MATCH_VNCLIPWX 0xbc004057
+#define MASK_VNCLIPWX 0xfc00707f
+#define MATCH_VNCLIPWI 0xbc003057
+#define MASK_VNCLIPWI 0xfc00707f
+#define MATCH_VFADDVV 0x00001057
+#define MASK_VFADDVV 0xfc00707f
+#define MATCH_VFADDVF 0x00005057
+#define MASK_VFADDVF 0xfc00707f
+#define MATCH_VFSUBVV 0x08001057
+#define MASK_VFSUBVV 0xfc00707f
+#define MATCH_VFSUBVF 0x08005057
+#define MASK_VFSUBVF 0xfc00707f
+#define MATCH_VFRSUBVF 0x9c005057
+#define MASK_VFRSUBVF 0xfc00707f
+#define MATCH_VFWADDVV 0xc0001057
+#define MASK_VFWADDVV 0xfc00707f
+#define MATCH_VFWADDVF 0xc0005057
+#define MASK_VFWADDVF 0xfc00707f
+#define MATCH_VFWSUBVV 0xc8001057
+#define MASK_VFWSUBVV 0xfc00707f
+#define MATCH_VFWSUBVF 0xc8005057
+#define MASK_VFWSUBVF 0xfc00707f
+#define MATCH_VFWADDWV 0xd0001057
+#define MASK_VFWADDWV 0xfc00707f
+#define MATCH_VFWADDWF 0xd0005057
+#define MASK_VFWADDWF 0xfc00707f
+#define MATCH_VFWSUBWV 0xd8001057
+#define MASK_VFWSUBWV 0xfc00707f
+#define MATCH_VFWSUBWF 0xd8005057
+#define MASK_VFWSUBWF 0xfc00707f
+#define MATCH_VFMULVV 0x90001057
+#define MASK_VFMULVV 0xfc00707f
+#define MATCH_VFMULVF 0x90005057
+#define MASK_VFMULVF 0xfc00707f
+#define MATCH_VFDIVVV 0x80001057
+#define MASK_VFDIVVV 0xfc00707f
+#define MATCH_VFDIVVF 0x80005057
+#define MASK_VFDIVVF 0xfc00707f
+#define MATCH_VFRDIVVF 0x84005057
+#define MASK_VFRDIVVF 0xfc00707f
+#define MATCH_VFWMULVV 0xe0001057
+#define MASK_VFWMULVV 0xfc00707f
+#define MATCH_VFWMULVF 0xe0005057
+#define MASK_VFWMULVF 0xfc00707f
+#define MATCH_VFMADDVV 0xa0001057
+#define MASK_VFMADDVV 0xfc00707f
+#define MATCH_VFMADDVF 0xa0005057
+#define MASK_VFMADDVF 0xfc00707f
+#define MATCH_VFNMADDVV 0xa4001057
+#define MASK_VFNMADDVV 0xfc00707f
+#define MATCH_VFNMADDVF 0xa4005057
+#define MASK_VFNMADDVF 0xfc00707f
+#define MATCH_VFMSUBVV 0xa8001057
+#define MASK_VFMSUBVV 0xfc00707f
+#define MATCH_VFMSUBVF 0xa8005057
+#define MASK_VFMSUBVF 0xfc00707f
+#define MATCH_VFNMSUBVV 0xac001057
+#define MASK_VFNMSUBVV 0xfc00707f
+#define MATCH_VFNMSUBVF 0xac005057
+#define MASK_VFNMSUBVF 0xfc00707f
+#define MATCH_VFMACCVV 0xb0001057
+#define MASK_VFMACCVV 0xfc00707f
+#define MATCH_VFMACCVF 0xb0005057
+#define MASK_VFMACCVF 0xfc00707f
+#define MATCH_VFNMACCVV 0xb4001057
+#define MASK_VFNMACCVV 0xfc00707f
+#define MATCH_VFNMACCVF 0xb4005057
+#define MASK_VFNMACCVF 0xfc00707f
+#define MATCH_VFMSACVV 0xb8001057
+#define MASK_VFMSACVV 0xfc00707f
+#define MATCH_VFMSACVF 0xb8005057
+#define MASK_VFMSACVF 0xfc00707f
+#define MATCH_VFNMSACVV 0xbc001057
+#define MASK_VFNMSACVV 0xfc00707f
+#define MATCH_VFNMSACVF 0xbc005057
+#define MASK_VFNMSACVF 0xfc00707f
+#define MATCH_VFWMACCVV 0xf0001057
+#define MASK_VFWMACCVV 0xfc00707f
+#define MATCH_VFWMACCVF 0xf0005057
+#define MASK_VFWMACCVF 0xfc00707f
+#define MATCH_VFWNMACCVV 0xf4001057
+#define MASK_VFWNMACCVV 0xfc00707f
+#define MATCH_VFWNMACCVF 0xf4005057
+#define MASK_VFWNMACCVF 0xfc00707f
+#define MATCH_VFWMSACVV 0xf8001057
+#define MASK_VFWMSACVV 0xfc00707f
+#define MATCH_VFWMSACVF 0xf8005057
+#define MASK_VFWMSACVF 0xfc00707f
+#define MATCH_VFWNMSACVV 0xfc001057
+#define MASK_VFWNMSACVV 0xfc00707f
+#define MATCH_VFWNMSACVF 0xfc005057
+#define MASK_VFWNMSACVF 0xfc00707f
+#define MATCH_VFSQRTV 0x4c001057
+#define MASK_VFSQRTV 0xfc0ff07f
+#define MATCH_VFRSQRT7V 0x4c021057
+#define MASK_VFRSQRT7V 0xfc0ff07f
+#define MATCH_VFREC7V 0x4c029057
+#define MASK_VFREC7V 0xfc0ff07f
+#define MATCH_VFCLASSV 0x4c081057
+#define MASK_VFCLASSV 0xfc0ff07f
+#define MATCH_VFMINVV 0x10001057
+#define MASK_VFMINVV 0xfc00707f
+#define MATCH_VFMINVF 0x10005057
+#define MASK_VFMINVF 0xfc00707f
+#define MATCH_VFMAXVV 0x18001057
+#define MASK_VFMAXVV 0xfc00707f
+#define MATCH_VFMAXVF 0x18005057
+#define MASK_VFMAXVF 0xfc00707f
+#define MATCH_VFSGNJVV 0x20001057
+#define MASK_VFSGNJVV 0xfc00707f
+#define MATCH_VFSGNJVF 0x20005057
+#define MASK_VFSGNJVF 0xfc00707f
+#define MATCH_VFSGNJNVV 0x24001057
+#define MASK_VFSGNJNVV 0xfc00707f
+#define MATCH_VFSGNJNVF 0x24005057
+#define MASK_VFSGNJNVF 0xfc00707f
+#define MATCH_VFSGNJXVV 0x28001057
+#define MASK_VFSGNJXVV 0xfc00707f
+#define MATCH_VFSGNJXVF 0x28005057
+#define MASK_VFSGNJXVF 0xfc00707f
+#define MATCH_VMFEQVV 0x60001057
+#define MASK_VMFEQVV 0xfc00707f
+#define MATCH_VMFEQVF 0x60005057
+#define MASK_VMFEQVF 0xfc00707f
+#define MATCH_VMFNEVV 0x70001057
+#define MASK_VMFNEVV 0xfc00707f
+#define MATCH_VMFNEVF 0x70005057
+#define MASK_VMFNEVF 0xfc00707f
+#define MATCH_VMFLTVV 0x6c001057
+#define MASK_VMFLTVV 0xfc00707f
+#define MATCH_VMFLTVF 0x6c005057
+#define MASK_VMFLTVF 0xfc00707f
+#define MATCH_VMFLEVV 0x64001057
+#define MASK_VMFLEVV 0xfc00707f
+#define MATCH_VMFLEVF 0x64005057
+#define MASK_VMFLEVF 0xfc00707f
+#define MATCH_VMFGTVF 0x74005057
+#define MASK_VMFGTVF 0xfc00707f
+#define MATCH_VMFGEVF 0x7c005057
+#define MASK_VMFGEVF 0xfc00707f
+#define MATCH_VFMERGEVFM 0x5c005057
+#define MASK_VFMERGEVFM 0xfe00707f
+#define MATCH_VFMVVF 0x5e005057
+#define MASK_VFMVVF 0xfff0707f
+#define MATCH_VFCVTXUFV 0x48001057
+#define MASK_VFCVTXUFV 0xfc0ff07f
+#define MATCH_VFCVTXFV 0x48009057
+#define MASK_VFCVTXFV 0xfc0ff07f
+#define MATCH_VFCVTFXUV 0x48011057
+#define MASK_VFCVTFXUV 0xfc0ff07f
+#define MATCH_VFCVTFXV 0x48019057
+#define MASK_VFCVTFXV 0xfc0ff07f
+#define MATCH_VFCVTRTZXUFV 0x48031057
+#define MASK_VFCVTRTZXUFV 0xfc0ff07f
+#define MATCH_VFCVTRTZXFV 0x48039057
+#define MASK_VFCVTRTZXFV 0xfc0ff07f
+#define MATCH_VFWCVTXUFV 0x48041057
+#define MASK_VFWCVTXUFV 0xfc0ff07f
+#define MATCH_VFWCVTXFV 0x48049057
+#define MASK_VFWCVTXFV 0xfc0ff07f
+#define MATCH_VFWCVTFXUV 0x48051057
+#define MASK_VFWCVTFXUV 0xfc0ff07f
+#define MATCH_VFWCVTFXV 0x48059057
+#define MASK_VFWCVTFXV 0xfc0ff07f
+#define MATCH_VFWCVTFFV 0x48061057
+#define MASK_VFWCVTFFV 0xfc0ff07f
+#define MATCH_VFWCVTRTZXUFV 0x48071057
+#define MASK_VFWCVTRTZXUFV 0xfc0ff07f
+#define MATCH_VFWCVTRTZXFV 0x48079057
+#define MASK_VFWCVTRTZXFV 0xfc0ff07f
+#define MATCH_VFNCVTXUFW 0x48081057
+#define MASK_VFNCVTXUFW 0xfc0ff07f
+#define MATCH_VFNCVTXFW 0x48089057
+#define MASK_VFNCVTXFW 0xfc0ff07f
+#define MATCH_VFNCVTFXUW 0x48091057
+#define MASK_VFNCVTFXUW 0xfc0ff07f
+#define MATCH_VFNCVTFXW 0x48099057
+#define MASK_VFNCVTFXW 0xfc0ff07f
+#define MATCH_VFNCVTFFW 0x480a1057
+#define MASK_VFNCVTFFW 0xfc0ff07f
+#define MATCH_VFNCVTRODFFW 0x480a9057
+#define MASK_VFNCVTRODFFW 0xfc0ff07f
+#define MATCH_VFNCVTRTZXUFW 0x480b1057
+#define MASK_VFNCVTRTZXUFW 0xfc0ff07f
+#define MATCH_VFNCVTRTZXFW 0x480b9057
+#define MASK_VFNCVTRTZXFW 0xfc0ff07f
+#define MATCH_VREDSUMVS 0x00002057
+#define MASK_VREDSUMVS 0xfc00707f
+#define MATCH_VREDMAXVS 0x1c002057
+#define MASK_VREDMAXVS 0xfc00707f
+#define MATCH_VREDMAXUVS 0x18002057
+#define MASK_VREDMAXUVS 0xfc00707f
+#define MATCH_VREDMINVS 0x14002057
+#define MASK_VREDMINVS 0xfc00707f
+#define MATCH_VREDMINUVS 0x10002057
+#define MASK_VREDMINUVS 0xfc00707f
+#define MATCH_VREDANDVS 0x04002057
+#define MASK_VREDANDVS 0xfc00707f
+#define MATCH_VREDORVS 0x08002057
+#define MASK_VREDORVS 0xfc00707f
+#define MATCH_VREDXORVS 0x0c002057
+#define MASK_VREDXORVS 0xfc00707f
+#define MATCH_VWREDSUMUVS 0xc0000057
+#define MASK_VWREDSUMUVS 0xfc00707f
+#define MATCH_VWREDSUMVS 0xc4000057
+#define MASK_VWREDSUMVS 0xfc00707f
+#define MATCH_VFREDOSUMVS 0x0c001057
+#define MASK_VFREDOSUMVS 0xfc00707f
+#define MATCH_VFREDUSUMVS 0x04001057
+#define MASK_VFREDUSUMVS 0xfc00707f
+#define MATCH_VFREDMAXVS 0x1c001057
+#define MASK_VFREDMAXVS 0xfc00707f
+#define MATCH_VFREDMINVS 0x14001057
+#define MASK_VFREDMINVS 0xfc00707f
+#define MATCH_VFWREDOSUMVS 0xcc001057
+#define MASK_VFWREDOSUMVS 0xfc00707f
+#define MATCH_VFWREDUSUMVS 0xc4001057
+#define MASK_VFWREDUSUMVS 0xfc00707f
+#define MATCH_VMANDMM 0x66002057
+#define MASK_VMANDMM 0xfe00707f
+#define MATCH_VMNANDMM 0x76002057
+#define MASK_VMNANDMM 0xfe00707f
+#define MATCH_VMANDNMM 0x62002057
+#define MASK_VMANDNMM 0xfe00707f
+#define MATCH_VMXORMM 0x6e002057
+#define MASK_VMXORMM 0xfe00707f
+#define MATCH_VMORMM 0x6a002057
+#define MASK_VMORMM 0xfe00707f
+#define MATCH_VMNORMM 0x7a002057
+#define MASK_VMNORMM 0xfe00707f
+#define MATCH_VMORNMM 0x72002057
+#define MASK_VMORNMM 0xfe00707f
+#define MATCH_VMXNORMM 0x7e002057
+#define MASK_VMXNORMM 0xfe00707f
+#define MATCH_VCPOPM 0x40082057
+#define MASK_VCPOPM 0xfc0ff07f
+#define MATCH_VFIRSTM 0x4008a057
+#define MASK_VFIRSTM 0xfc0ff07f
+#define MATCH_VMSBFM 0x5000a057
+#define MASK_VMSBFM 0xfc0ff07f
+#define MATCH_VMSIFM 0x5001a057
+#define MASK_VMSIFM 0xfc0ff07f
+#define MATCH_VMSOFM 0x50012057
+#define MASK_VMSOFM 0xfc0ff07f
+#define MATCH_VIOTAM 0x50082057
+#define MASK_VIOTAM 0xfc0ff07f
+#define MATCH_VIDV 0x5008a057
+#define MASK_VIDV 0xfdfff07f
+#define MATCH_VMVXS 0x42002057
+#define MASK_VMVXS 0xfe0ff07f
+#define MATCH_VMVSX 0x42006057
+#define MASK_VMVSX 0xfff0707f
+#define MATCH_VFMVFS 0x42001057
+#define MASK_VFMVFS 0xfe0ff07f
+#define MATCH_VFMVSF 0x42005057
+#define MASK_VFMVSF 0xfff0707f
+#define MATCH_VSLIDEUPVX 0x38004057
+#define MASK_VSLIDEUPVX 0xfc00707f
+#define MATCH_VSLIDEUPVI 0x38003057
+#define MASK_VSLIDEUPVI 0xfc00707f
+#define MATCH_VSLIDEDOWNVX 0x3c004057
+#define MASK_VSLIDEDOWNVX 0xfc00707f
+#define MATCH_VSLIDEDOWNVI 0x3c003057
+#define MASK_VSLIDEDOWNVI 0xfc00707f
+#define MATCH_VSLIDE1UPVX 0x38006057
+#define MASK_VSLIDE1UPVX 0xfc00707f
+#define MATCH_VSLIDE1DOWNVX 0x3c006057
+#define MASK_VSLIDE1DOWNVX 0xfc00707f
+#define MATCH_VFSLIDE1UPVF 0x38005057
+#define MASK_VFSLIDE1UPVF 0xfc00707f
+#define MATCH_VFSLIDE1DOWNVF 0x3c005057
+#define MASK_VFSLIDE1DOWNVF 0xfc00707f
+#define MATCH_VRGATHERVV 0x30000057
+#define MASK_VRGATHERVV 0xfc00707f
+#define MATCH_VRGATHERVX 0x30004057
+#define MASK_VRGATHERVX 0xfc00707f
+#define MATCH_VRGATHERVI 0x30003057
+#define MASK_VRGATHERVI 0xfc00707f
+#define MATCH_VRGATHEREI16VV 0x38000057
+#define MASK_VRGATHEREI16VV 0xfc00707f
+#define MATCH_VCOMPRESSVM 0x5e002057
+#define MASK_VCOMPRESSVM 0xfe00707f
+#define MATCH_VMV1RV 0x9e003057
+#define MASK_VMV1RV 0xfe0ff07f
+#define MATCH_VMV2RV 0x9e00b057
+#define MASK_VMV2RV 0xfe0ff07f
+#define MATCH_VMV4RV 0x9e01b057
+#define MASK_VMV4RV 0xfe0ff07f
+#define MATCH_VMV8RV 0x9e03b057
+#define MASK_VMV8RV 0xfe0ff07f
+#define MATCH_VDOTVV 0xe4000057
+#define MASK_VDOTVV 0xfc00707f
+#define MATCH_VDOTUVV 0xe0000057
+#define MASK_VDOTUVV 0xfc00707f
+#define MATCH_VFDOTVV 0xe4001057
+#define MASK_VFDOTVV 0xfc00707f
+/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
#define CSR_UTVEC 0x5
#define CSR_UCAUSE 0x42
#define CSR_UTVAL 0x43
#define CSR_UIP 0x44
-#define CSR_FFLAGS 0x1
-#define CSR_FRM 0x2
-#define CSR_FCSR 0x3
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_MHPMEVENT29 0x33d
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
-#define CSR_TSELECT 0x7a0
-#define CSR_TDATA1 0x7a1
-#define CSR_TDATA2 0x7a2
-#define CSR_TDATA3 0x7a3
-#define CSR_DCSR 0x7b0
-#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH0 0x7b2
-#define CSR_DSCRATCH1 0x7b3
#define CSR_HSTATUS 0x200
#define CSR_HEDELEG 0x202
#define CSR_HIDELEG 0x203
#define CSR_MDBOUND 0x385
#define CSR_MSCOUNTEREN 0x321
#define CSR_MHCOUNTEREN 0x322
-
-#define CAUSE_MISALIGNED_FETCH 0x0
-#define CAUSE_FAULT_FETCH 0x1
-#define CAUSE_ILLEGAL_INSTRUCTION 0x2
-#define CAUSE_BREAKPOINT 0x3
-#define CAUSE_MISALIGNED_LOAD 0x4
-#define CAUSE_FAULT_LOAD 0x5
-#define CAUSE_MISALIGNED_STORE 0x6
-#define CAUSE_FAULT_STORE 0x7
-#define CAUSE_USER_ECALL 0x8
-#define CAUSE_SUPERVISOR_ECALL 0x9
-#define CAUSE_HYPERVISOR_ECALL 0xa
-#define CAUSE_MACHINE_ECALL 0xb
-#endif
+/* Unprivileged CSR addresses. */
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_TINFO 0x7a4
+#define CSR_TCONTROL 0x7a5
+#define CSR_MCONTEXT 0x7a8
+#define CSR_SCONTEXT 0x7aa
+#define CSR_SEED 0x015
+#define CSR_VSTART 0x008
+#define CSR_VXSAT 0x009
+#define CSR_VXRM 0x00a
+#define CSR_VCSR 0x00f
+#define CSR_VL 0xc20
+#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
+#endif /* RISCV_ENCODING_H */
#ifdef DECLARE_INSN
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
DECLARE_INSN(sh, MATCH_SH, MASK_SH)
DECLARE_INSN(sw, MATCH_SW, MASK_SW)
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE)
DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
+DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
+DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
+DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
+DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
+DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
+DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
+DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
+DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
+DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
+DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
+DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
+DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
+DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
+DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
+DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
+DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
+DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
+DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
+DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
+DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
+DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
+DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
+DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
+DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
+DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
+DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
+DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
+DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
+DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
+DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
+DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
+DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
+DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
+DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
+DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
+DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
+DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
+DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
+DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
-DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
-DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
-DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
-DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
-DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
-DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
-DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
-DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
-DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
-DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
-DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
-DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
-DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
-DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
-DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
-DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
-DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
-DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
-DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
-DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-#endif
+#endif /* DECLARE_INSN */
#ifdef DECLARE_CSR
+/* Privileged CSRs. */
DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
-DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
+/* Dropped CSRs. */
DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
-#endif
+/* Unprivileged CSRs. */
+DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_ZKR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+#endif /* DECLARE_CSR */
#ifdef DECLARE_CSR_ALIAS
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
-DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P11)
-#endif
-#ifdef DECLARE_CAUSE
-DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
-DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
-DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
-DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
-DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
-DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
-DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
-DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
-DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
-DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
-DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
-DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
-#endif
+DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(mcontrol, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(icount, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+#endif /* DECLARE_CSR_ALIAS */
projects / binutils-gdb.git / blobdiff