#define OP_SH_RS2 20
#define OP_MASK_RS1 0x1f
#define OP_SH_RS1 15
-#define OP_MASK_RS3 0x1f
+#define OP_MASK_RS3 0x1fU
#define OP_SH_RS3 27
#define OP_MASK_RD 0x1f
#define OP_SH_RD 7
#define OP_MASK_RL 0x1
#define OP_SH_RL 25
-#define OP_MASK_CUSTOM_IMM 0x7f
+#define OP_MASK_CUSTOM_IMM 0x7fU
#define OP_SH_CUSTOM_IMM 25
-#define OP_MASK_CSR 0xfff
+#define OP_MASK_CSR 0xfffU
#define OP_SH_CSR 20
#define OP_MASK_FUNCT3 0x7
#define OP_SH_FUNCT3 12
-#define OP_MASK_FUNCT7 0x7f
+#define OP_MASK_FUNCT7 0x7fU
#define OP_SH_FUNCT7 25
#define OP_MASK_FUNCT2 0x3
#define OP_SH_FUNCT2 25
ISA_SPEC_CLASS_20191213
};
+#define RISCV_UNKNOWN_VERSION -1
+
/* This structure holds version information for specific ISA. */
struct riscv_ext_version
{
const char *name;
enum riscv_isa_spec_class isa_spec_class;
- unsigned int major_version;
- unsigned int minor_version;
+ int major_version;
+ int minor_version;
};
/* All RISC-V CSR belong to one of these classes. */