i965: add more Haswell PCI IDs

[mesa.git] / include / pci_ids / i965_pci_ids.h

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index e38f8d2228379d122f040b3c548a5aa445e8dc38..09dca5b0ed6b0194212e55ef8d35f0c9bad18f54 100644 (file)
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -28,6 +28,37 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)
 CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2)
 CHIPSET(0x0402, HASWELL_GT1, hsw_gt1)
 CHIPSET(0x0412, HASWELL_GT2, hsw_gt2)
+CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2)
 CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1)
 CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2)
-CHIPSET(0x0A16, HASWELL_M_ULT_GT2, hsw_gt2)
+CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1)
+CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2)
+CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1)
+CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2)
+CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1)
+CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2)
+CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1)
+CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2)
+CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1)
+CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2)
+CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1)
+CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2)
+CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1)
+CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2)
+CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1)
+CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2)
+CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1)
+CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2)
+CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1)
+CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2)
+CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)