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[libreriscv.git] / index.mdwn

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@@ -1,4 +1,6 @@
-# Welcome to Libre-RISC-V.
+# Welcome to Libre-SoC!
+
+Libre-RISCV is an effort to develop an completely open/Libre SOC that is open to the bedrock!
 
 This is a publicly editable wiki.
 
@@ -14,21 +16,23 @@ This is the sitemap: [[sitemap]]
 
 This process probably needs some improvement, but the basic 
 idea is to join the [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev), introduce yourself,
-and read through [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/).
+and read through [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/) and the [[charter]].
 
 The next thing you should do is read through the [bugs list](http://bugs.libre-riscv.org) and see if there are any bugs that pique your interest.
 
-We do have funding available upon fixing bugs - we are also working on procuring more funding.
+We do have funding available (see [[nlnet]]) upon completion of issues - we are also working on procuring more funding which gets the project to nanometre scale tapeout.
 
 ## Needed Skills
 
 Most labor is currently being applied to developing the GPU portion of the LibreSOC.
 
-We mainly need HDL engineers at the moment. Particularly those familiar with nMigen.
+The highest priority needed at the moment is a c++ engineer to work on a MESA 3D driver. This will begin life as similar to SwiftShader however retaining the vectorisation and predication intrinsics.
+
+Medium to long-term we need HDL engineers. Particularly those familiar with nMigen or just python.  Most of the techniques being used require software engineering skills (OO design, polymorphism) than they do more traditional HDL programming skills. Basically if you have experience in 2 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level design. See [[HDL_workflow]]
 
-Also, individuals with experience in formal verification are quite welcome.
+Also, individuals with experience in formal mathematical verification are quite welcome.
 
-TODO: add a list of upcoming project tasks/milestones
+TODO: add a list of upcoming project tasks/milestones (link to bugtracker).
 
 # Resources
 
@@ -38,6 +42,7 @@ TODO: add a list of upcoming project tasks/milestones
   may be cloned publicly with
   git clone https://git.libre-riscv.org/git/repositoryname.git
 * Bugzilla at <http://bugs.libre-riscv.org/>
+* Kazan (Vulkan driver) at <https://salsa.debian.org/Kazan-team/kazan>
 * Further Information [[resources]]
 
 # Main Pages