(no commit message)

[libreriscv.git] / index.mdwn

diff --git a/index.mdwn b/index.mdwn
index 5e8a4865e08962eb344e1957a4b4a7fd2893917f..317b1aae66e53adff34db7d2d08b676be163b177 100644 (file)
--- a/index.mdwn
+++ b/index.mdwn
@@ -75,7 +75,7 @@ funding and always appreciate more!  If you are a Corporation or an
 individual you can donate tax-free to NLNet, and they can in turn gift
 our developers.  Contact lkcl@lkcl.net for more information.
 
-# How Can I Help as a Developer?
+# How Can I Help as a Developer? <a name="help_as_developer"></a>
 
 If you want to write code with us (and receive donations from NLNet
 for doing so), keep reading.  If you want to *learn*
@@ -126,6 +126,7 @@ step you will have needed to install yosys:
     git clone https://git.libre-soc.org/git/nmigen.git
     git clone https://git.libre-soc.org/git/nmigen-soc.git
     git clone https://git.libre-soc.org/git/nmutil.git
+    git clone https://git.libre-soc.org/git/openpower-isa.git
     git clone https://git.libre-soc.org/git/c4m-jtag.git
     git clone https://git.libre-soc.org/git/ieee754fpu.git
     git clone https://git.libre-soc.org/git/soc.git
@@ -133,8 +134,9 @@ step you will have needed to install yosys:
     cd nmigen; python setup.py develop; cd ..
     cd nmigen-soc; python setup.py develop; cd ..
     cd c4m-jtag; python setup.py develop; cd ..
-    cd nmutil; make install; cd ..
-    cd ieee754fpu; make install; cd ..
+    cd nmutil; make develop; cd ..
+    cd openpower-isa; make develop; cd ..
+    cd ieee754fpu; make develop; cd ..
     cd soc; make gitupdate; make develop
     
     python3 src/soc/decoder/power_decoder.py