-# Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)!
+# Welcome to LibreSoC
-LibreSOC strives to deliver a fully capable and competitive Libre integrated System on Chip. We want to maximize the degree of trust a customer can place in his or her processor. We do this by providing the customer the freedom to study, modify, and redistribute the SOC source from HDL to VLSI.
-
-Right now, we're targeting a (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC.
-
-## Why a Libre SOC?
-
-Its quite hard to guarantee that a performant processors(think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com).
-
-There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline(this doesn’t even consider out of order execution).
-
-Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them.
-
-Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc.
-
-## Benefits: Privacy, Safety-Critical, Peace of Mind...
-Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html).
-
-There is a very real need for reliable safety critical processors(think airplane, smart car, pacemaker...).
-LibreSOC poses to you that it is impossible to trust a processor in a safety critical environment without both access
-to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they
-expect. An ISA level simulator is no longer satisfactory.
-
-Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.
-
-## Still Have Questions?
-Read about the business and practical benefits of a LibreSOC below.
-
-[[why_a_libresoc]]
+> We're gonna build a chip. A fast chip. A chip with lots of peripherals. And a gpu. Here have the source code.
+Sounds cool? Learn more [here](who_we_are)
# Join us in Realizing the First Market Ready LibreSOC!
-First. join the
+1. First, join the
[mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
introduce yourself, and read through
[recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
and the [[charter]].
-The next thing you should do is read through the [bugs
+2. The next thing you should do is read through the [bugs
list](http://bugs.libre-riscv.org) and see if there are any bugs that
pique your interest.
-We do have funding available (see [[nlnet]]) upon completion of issues -
+3. After that, go ahead and take a look at the resources section below.
+Try and clone a repository with ``git clone https://git.libre-riscv.org/git/repositoryname.git``
+
+4. If you plan to do HDL work, you should familiarize yourself with our [[HDL_workflow]].
+
+5. We do have funding available (see [[nlnet]]) upon completion of issues -
we are also working on procuring more funding which gets the project to
nanometre scale tapeout.
-After all this, if you feel that Libre-SoC is a good cause that
+6. After all this, if you feel that Libre-SoC is a good cause that
you would like to contribute to, add yourself to the [[current_members]]
page, fill in some information about yourself, and join the mailing list
and say hello.
# Resources
-* Mailing Lists <http://lists.libre-riscv.org> -
- Archives at <http://lists.libre-riscv.org/pipermail>
-* Git repositories <http://git.libre-riscv.org>
- may be cloned publicly with
- git clone https://git.libre-riscv.org/git/repositoryname.git
-* Bugzilla at <http://bugs.libre-riscv.org/>
-* Kazan (Vulkan driver) at <https://salsa.debian.org/Kazan-team/kazan>
-* Further Information [[resources]]
+| Resource | Link |
+| --- | --- |
+| Bugs and Tasks | <http://bugs.libre-riscv.org/> |
+| Mailing Lists | <http://lists.libre-riscv.org> |
+| Archives | <http://lists.libre-riscv.org/pipermail> |
+| Git repositories | <http://git.libre-riscv.org> |
+| Kazan (Vulkan driver) | <https://salsa.debian.org/Kazan-team/kazan> |
+| Further Information | [[resources]] |
# Main Pages
projects / libreriscv.git / blobdiff