update priorities

[libreriscv.git] / index.mdwn

diff --git a/index.mdwn b/index.mdwn
index 2c65ebdc272733fdd04ff3e8823cf6ecd54c1351..a56f63f915b19849b054f277dc42da4602a77156 100644 (file)
--- a/index.mdwn
+++ b/index.mdwn
@@ -64,7 +64,8 @@ funding and always appreciate more!  If you are a Corporation or an
 individual you can donate tax-free to NLNet, and they can in turn gift
 our developers.  Contact lkcl@lkcl.net for more information.
 
-If you want to write code with us, keep reading.  If you want to *learn*
+If you want to write code with us (and receive donations from NLNet
+for doing so), keep reading.  If you want to *learn*
 so that you can write code with us, see below.  If there is anything else,
 just get in touch on the list, there is plenty to do.
 
@@ -77,10 +78,8 @@ happy with it and agree to it.
 2. The next thing you should do is read through the [bugs
 list](http://bugs.libre-riscv.org) and see if there are any bugs that
 pique your interest.
-3. After that, go ahead and take a look at the
-   [git repositories](https://git.libre-riscv.org).
-Try and clone a repository with
-``git clone https://git.libre-riscv.org/git/repositoryname.git``
+3. After that, go ahead and take a look at the    [git repositories](https://git.libre-riscv.org).
+
 4. If you plan to do HDL work, you should familiarize yourself with our
    [[HDL_workflow]].
 5. We do have funding available (see [[nlnet]]) upon completion of issues -
@@ -93,6 +92,32 @@ nanometre scale tapeout.
 
 Also note that you can edit this wiki.  You can experiment in the [[Sandbox]].
 
+## Quick peek at the code
+
+Here is an example process of how to play with the soc code:
+
+<div class="jumbotron">
+pip3 install virtualenv requests <br />
+mkdir ~/.virtualenvs && cd ~/.virtualenvs <br />
+python3 -m venv libresoc <br />
+source ~/.virtualenvs/bin/activate <br />
+<br />
+cd ~; mkdir libresoc; cd libresoc <br />
+git clone https://git.libre-riscv.org/git/nmutil.git <br />
+git clone https://git.libre-riscv.org/git/ieee754fpu.git <br />
+git clone --recursive https://git.libre-riscv.org/git/soc.git <br />
+<br />
+cd nmutil; pip3 install -e .; cd .. <br />
+cd ieee754fpu; pip3 install -e .; cd .. <br />
+cd soc; pip3 install -e .; cd .. <br />
+<br />
+# play with the decoder <br />
+python3 soc/src/soc/decoder/power_decoder.py <br />
+<br />
+# after installing yosys <br />
+yosys -p "read_ilang decoder.il; show dec31" <br />
+</div>
+
 ## How can I learn?
 
 The whole purpose of this project is to be a learning environment as well
@@ -110,17 +135,18 @@ can also benefit (and you have a place to remember them, too).
 Most labor is currently being applied to developing the GPU portion of
 the Libre-SOC.
 
-The highest priority needed at the moment is a c++ engineer to work on
-a MESA 3D driver. This will begin life similar to SwiftShader however
-retaining the vectorisation and predication intrinsics as well as hardware
-accelerated opcodes (all of which SwiftShader lacks)
-
-Medium to long-term we need HDL engineers. Particularly those familiar
+Our highest priority short-term and medium-term: we need HDL engineers.
+Particularly those familiar
 with nMigen or just python.  Most of the techniques being used require
 software engineering skills (OO design, polymorphism) than they do more
 traditional HDL programming skills. Basically if you have experience in 2
 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
 design. See [[HDL_workflow]]
 
+We also need to find a c++ engineer with compiler experience to work on
+a MESA 3D driver. This will begin life similar to SwiftShader however
+retaining the vectorisation and predication intrinsics as well as hardware
+accelerated opcodes (all of which SwiftShader lacks)
+
 Also, individuals with experience in formal mathematical verification
 are quite welcome.