-# Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)!
+# Welcome to LibreSOC
-LibreSOC strives to deliver a fully capable and competitive mass volume Libre integrated System on Chip for use in chromebooks, smartphone, tablets and industrial boards. We want to maximize the degree of trust a customer can place in their processor. We do this by providing the customer the freedom to study, modify, and redistribute the the bootloader and Operating System full source code *and* the full SoC source from HDL to VLSI.
+> We're building a chip. A fast chip. A safe chip. A trusted chip.
-Right now, we're targeting a (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC.
+> A chip with lots of peripherals. And a VPU. And a 3D GPU...
-See our [[3d_gpu/mission_statement]]
+> Oh and here, have the source code...
-## Why a Libre SOC?
+Sounds cool? Learn more about the [why](why_a_libresoc) behind LibreSOC
+and [our mission](The_Mission).
-Its quite hard to guarantee that a performant processors (think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com).
+# Our Team
-There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline (this doesn’t even consider out of order execution).
+We are proud of our talented and diverse [team](about_us).
-Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them.
+# How Can I Help?
-Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire LibreSOC.
+If you would like to fund us, see [[funding]]. We currently have some
+funding and always appreciate more! If you are a Corporation or an
+individual you can donate tax-free to NLNet, and they can in turn gift
+our developers. Contact lkcl@lkcl.net for more information.
-## Benefits: Privacy, Safety-Critical, Peace of Mind...
-Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html).
-
-There is a very real need for reliable safety critical processors (think airplane, smart car, nuclear power plant, pacemaker...).
-LibreSOC posits that it is impossible to trust a processor in a safety critical environment without both access
-to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they
-expect. An ISA level simulator is no longer satisfactory.
-
-Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.
-
-## Still Have Questions?
-
-Read about the business and practical benefits of a LibreSOC below.
-
-[[why_a_libresoc]]
-
-# Join us in Realizing the First Market Ready LibreSOC!
+If you want to write code with us, keep reading.
1. First, join the
[mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
introduce yourself, and read through
[recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
and the [[charter]].
-
2. The next thing you should do is read through the [bugs
list](http://bugs.libre-riscv.org) and see if there are any bugs that
pique your interest.
-
-3. After that, go ahead and take a look at the [resources](#resources) section below.
-Try and clone a repository with ``git clone https://git.libre-riscv.org/git/repositoryname.git``
-
-4. If you plan to do HDL work, you should familiarize yourself with our [[HDL_workflow]].
-
+3. After that, go ahead and take a look at the resources section below.
+Try and clone a repository with
+``git clone https://git.libre-riscv.org/git/repositoryname.git``
+4. If you plan to do HDL work, you should familiarize yourself with our
+ [[HDL_workflow]].
5. We do have funding available (see [[nlnet]]) upon completion of issues -
we are also working on procuring more funding which gets the project to
nanometre scale tapeout.
-
-6. After all this, if you feel that Libre-SoC is a good cause that
-you would like to contribute to, add yourself to the [[current_members]]
+6. After all this, if you feel that Libre-SoC is a something that
+you would like to contribute to, add yourself to the [current_members](about_us)
page, fill in some information about yourself, and join the mailing list
and say hello.
The highest priority needed at the moment is a c++ engineer to work on
a MESA 3D driver. This will begin life similar to SwiftShader however
-retaining the vectorisation and predication intrinsics as well as hardware accelerated opcodes (all of which SwiftShader lacks)
+retaining the vectorisation and predication intrinsics as well as hardware
+accelerated opcodes (all of which SwiftShader lacks)
Medium to long-term we need HDL engineers. Particularly those familiar
with nMigen or just python. Most of the techniques being used require
| Archives | <http://lists.libre-riscv.org/pipermail> |
| Git repositories | <http://git.libre-riscv.org> |
| Kazan (Vulkan driver) | <https://salsa.debian.org/Kazan-team/kazan> |
+| Standards | [[standards]] |
| Further Information | [[resources]] |
# Main Pages
* [[ztrans_proposal]]
* [[simple_v_extension/specification/mv.x]]
* [[simple_v_extension/specification/ld.x]]
+* [[future_feature_proposals]]
* Specifications and [[resources]]
# Spike Emulator
[1]: https://libre-riscv.org/3d_gpu/spike_sv/
-# Current Members
-
-[[current_members]]
-
-# Wiki Structure
-
-This is a publicly editable wiki.
-
-All wikis are supposed to have a [[SandBox]], so this one does too.
-
-This wiki is powered by [[ikiwiki]].
-
-This is the sitemap: [[sitemap]]
projects / libreriscv.git / blobdiff