-# Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)!
-
-LibreSOC strives to deliver a fully capable and competitive mass volume Libre integrated System on Chip for use in chromebooks, smartphone, tablets and industrial boards. We want to maximize the degree of trust a customer can place in their processor. We do this by providing the customer the freedom to study, modify, and redistribute the the bootloader and Operating System full source code *and* the full SoC source from HDL to VLSI.
-
-Right now, we're targeting a (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC.
-
-See our [[3d_gpu/mission_statement]]
-
-## Why a Libre SOC?
-
-Its quite hard to guarantee that a performant processors (think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com).
-
-There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline (this doesn’t even consider out of order execution).
-
-Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them.
-
-Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire LibreSOC.
-
-## Benefits: Privacy, Safety-Critical, Peace of Mind...
-Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html).
-
-There is a very real need for reliable safety critical processors (think airplane, smart car, nuclear power plant, pacemaker...).
-LibreSOC posits that it is impossible to trust a processor in a safety critical environment without both access
-to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they
-expect. An ISA level simulator is no longer satisfactory.
-
-Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.
-
-## Still Have Questions?
-
-Read about the business and practical benefits of a LibreSOC below.
-
-[[why_a_libresoc]]
-
-# Join us in Realizing the First Market Ready LibreSOC!
-
-First, join the
-[mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
-introduce yourself, and read through
-[recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
-and the [[charter]].
-
-The next thing you should do is read through the [bugs
-list](http://bugs.libre-riscv.org) and see if there are any bugs that
-pique your interest.
-
-We do have funding available (see [[nlnet]]) upon completion of issues -
-we are also working on procuring more funding which gets the project to
-nanometre scale tapeout.
-
-After all this, if you feel that Libre-SoC is a good cause that
-you would like to contribute to, add yourself to the [[current_members]]
-page, fill in some information about yourself, and join the mailing list
-and say hello.
-
-Also note that you can edit this wiki. See the last section of this page.
+<div class="jumbotron">
+ <h1 class="display-5">Welcome to Libre-SOC</h1>
+<blockquote>
+ <p>We're building a chip. A fast chip. A safe chip. A trusted chip.</p>
+
+ <p>A chip with lots of peripherals. And a VPU. And a 3D GPU...</p>
+
+ <p>Oh and here, have the <a href="http://git.libre-riscv.org">source code</a>...</p>
+</blockquote>
+ <hr class="my-4">
+
+<h2 class="display-5">Why should I care?</h2>
+
+With Libre-SOC, you can take complex algorithms usually intended for
+power hungry servers with big fat GPUs, and run them on tiny devices
+like smartwatches, cellphones, and pocket drones without changing your
+code at all.
+
+ <hr class="my-4">
+
+<h2 class="display-5">Hasn't Somebody Already Done This?</h2>
+
+To the best of our knowledge, no. The closest systems would be ARM Cortex
+devices which currently offer mediocre GPU and OpenCL support. Often
+times, it is quite difficult for customers to get their hands on the
+drivers and install them due to their locked down nature. Libre-SOC is
+providing our own Free/Libre drivers. Easy as 1, 2, 3!
+
+ <hr class="my-4">
+
+<h2 class="display-5">Does Open Hardware Really Work?</h2>
+<p>A few names come to mind:</p>
+
+<ul>
+<li><a href="https://www.raspberrypi.org">Raspberry Pi</a></li>
+<li><a href="https://www.arduino.cc">Arduino</a></li>
+<li><a href="https://www.raptorcs.com">Raptor Computing Systems</a></li>
+<li><a href="https://www.bitcraze.io">CrazyFlie</a></li>
+<li><a href="https://www.scopefun.com">ScopeFun</a></li>
+</ul>
+
+ <p class="lead">
+ <a class="btn btn-primary btn-lg" href="https://libre-soc.org/why_a_libresoc/" role="button">Learn more</a>
+
+</div>
+
+
+
+# Our Team
+
+We are proud of our talented and diverse [team](about_us).
+
+# Our sponsors and partners
+
+* [Purism](http://puri.sm) donates to us through [NLNet](nlnet)
+ charitable gifting
+* [Raptor CS](http://raptorcs.com) has given us access to a powerful
+ 18-core 128 GB RAM TALOS II workstation, online.
+* [Raptor Engineering](https://raptorengineering.com) is providing
+ additional assistance including access to an [[shakti/m_class/LPC]]
+ interface (more to come)
+* [MarketNext](http://marketnext.org) is helping us connect to developer
+ resources in Emerging markets, for completion of NLNet-funded tasks.
+ See the upcoming [Hackathon](https://www.youtube.com/embed/Px6eakWja3Q"),
+ deadline May 15th
+* The [[PowerPC Notebook]] Project
+
+# How Can I Help?
+
+If you would like to fund us, see [[funding]]. We currently have some
+funding and always appreciate more! If you are a Corporation or an
+individual you can donate tax-free to NLNet, and they can in turn gift
+our developers. Contact lkcl@lkcl.net for more information.
+
+# How Can I Help as a Developer?
+
+If you want to write code with us (and receive donations from NLNet
+for doing so), keep reading. If you want to *learn*
+so that you can write code with us, see "How can I learn" section,
+below. If there is anything else,
+just get in touch on the list, there is plenty to do.
+
+1. First, join the
+ [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
+ introduce yourself (people will happily say "hello" back"). Read through
+ [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
+ and the [[charter]], and let everyone know, on the list that you're
+ happy with it and agree to it.
+2. The next thing you should do is read through the
+ [bugs list](http://bugs.libre-riscv.org) and
+ see if there are any bugs that pique your interest.
+ A fascinating way to do that is to view the
+ [dependency graph](https://bugs.libre-soc.org/showdependencygraph.cgi?id=1&display=web&rankdir=LR)
+3. After that, go ahead and take a look at the
+ [git repositories](https://git.libre-riscv.org).
+4. If you plan to do HDL work, you should familiarize yourself with our
+ [[HDL_workflow]]. If you would like to help with the ASIC layout,
+ see [[HDL_workflow/coriolis2]]
+5. We do have funding available (see [[nlnet]]) upon completion of issues -
+ we are also working on procuring more funding which gets the project to
+ nanometre scale tapeout.
+6. After all this, if you feel that Libre-SOC is a something
+ that you would like to contribute to, add yourself to the
+ [current_members](about_us) page, fill in some information about yourself,
+ and join the mailing list and say hello.
+
+Also note that you can edit this wiki. You can experiment in the [[Sandbox]].
+
+## Quick peek at the code
+
+Here is an example process of how to play with the soc code:
+
+ pip3 install virtualenv requests
+ mkdir ~/.virtualenvs && cd ~/.virtualenvs
+ python3 -m venv libresoc
+ source ~/.virtualenvs/libresoc/bin/activate
+
+ cd ~; mkdir libresoc; cd libresoc
+ git clone https://git.libre-soc.org/git/nmutil.git
+ git clone https://git.libre-soc.org/git/ieee754fpu.git
+ git clone https://git.libre-soc.org/git/soc.git
+
+ cd nmutil; make install; cd ..
+ cd ieee754fpu; make install; cd ..
+ cd soc; make gitupdate; make install; cd ..
+
+ python3 soc/src/soc/decoder/power_decoder.py
+ yosys -p "read_ilang decoder.il; show dec31"
+
+## How can I learn?
+
+The whole purpose of this project is to be a learning environment as well
+as an actual business. If you want to learn how to do ASIC design, with
+a view to contributing or starting your own ASIC business, start here:
+[[3d_gpu/tutorial]]. Yes, really: do not let anyone tell you that you
+can't learn this stuff too.
+
+Along the way, if you find any [[resources]] or links that you found
+particularly helpful, please add them to that page so that other people
+can also benefit (and you have a place to remember them, too).
## Needed Skills
Most labor is currently being applied to developing the GPU portion of
-the Libre-SoC.
+the Libre-SOC.
-The highest priority needed at the moment is a c++ engineer to work on
-a MESA 3D driver. This will begin life similar to SwiftShader however
-retaining the vectorisation and predication intrinsics as well as hardware accelerated opcodes (all of which SwiftShader lacks)
-
-Medium to long-term we need HDL engineers. Particularly those familiar
+Our highest priority short-term and medium-term: we need HDL engineers.
+Particularly those familiar
with nMigen or just python. Most of the techniques being used require
software engineering skills (OO design, polymorphism) than they do more
traditional HDL programming skills. Basically if you have experience in 2
of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
design. See [[HDL_workflow]]
+We also need to find a c++ engineer with compiler experience to work on
+a MESA 3D driver. This will begin life similar to SwiftShader however
+retaining the vectorisation and predication intrinsics as well as hardware
+accelerated opcodes (all of which SwiftShader lacks)
+
Also, individuals with experience in formal mathematical verification
are quite welcome.
-TODO: add a list of upcoming project tasks/milestones (link to
-bugtracker).
-
-# Resources
-
-| Resource | Link |
-| --- | --- |
-| Bugs and Tasks | <http://bugs.libre-riscv.org/> |
-| Mailing Lists | <http://lists.libre-riscv.org> |
-| Archives | <http://lists.libre-riscv.org/pipermail> |
-| Git repositories | <http://git.libre-riscv.org> |
-| Kazan (Vulkan driver) | <https://salsa.debian.org/Kazan-team/kazan> |
-| Further Information | [[resources]] |
-
-# Main Pages
-
-* Libre-SoC [[charter]]
-* [[shakti/m_class]]
-* [[alt_rvp]]
-* [[3d_gpu]]
-* [[vpu]]
-* [[simple_v_extension]]
-* [[zfpacc_proposal]]
-* [[ztrans_proposal]]
-* [[simple_v_extension/specification/mv.x]]
-* [[simple_v_extension/specification/ld.x]]
-* Specifications and [[resources]]
-
-# Spike Emulator
-* [Set-Up Instructions][1]
-
-[1]: https://libre-riscv.org/3d_gpu/spike_sv/
-
-# Current Members
-
-[[current_members]]
-
-# Wiki Structure
-
-This is a publicly editable wiki.
-
-All wikis are supposed to have a [[SandBox]], so this one does too.
-
-This wiki is powered by [[ikiwiki]].
+# Documentation
-This is the sitemap: [[sitemap]]
+ - [Source Code](/Documentation/index)
+ - [Architecture](3d_gpu/architecture)
projects / libreriscv.git / blobdiff