(no commit message)

[libreriscv.git] / index.mdwn

diff --git a/index.mdwn b/index.mdwn
index a4a87f69d1845ed6356d1d3cdc1454e0a4e95144..f9806a84fb36066ea65ea934b11977cbc07c624c 100644 (file)
--- a/index.mdwn
+++ b/index.mdwn
@@ -116,13 +116,13 @@ Here is an example process of how to play with the soc code:
     source ~/.virtualenvs/libresoc/bin/activate
     
     cd ~; mkdir libresoc; cd libresoc
-    git clone https://git.libre-riscv.org/git/nmutil.git
-    git clone https://git.libre-riscv.org/git/ieee754fpu.git
-    git clone https://git.libre-riscv.org/git/soc.git
+    git clone https://git.libre-soc.org/git/nmutil.git
+    git clone https://git.libre-soc.org/git/ieee754fpu.git
+    git clone https://git.libre-soc.org/git/soc.git
     
-    cd nmutil; pip3 install -e .; cd ..
-    cd ieee754fpu; pip3 install -e .; cd ..
-    cd soc; git submodule init; git submodule update; pip3 install -e .; cd ..
+    cd nmutil; make install; cd ..
+    cd ieee754fpu; make install; cd ..
+    cd soc; make gitupdate; make install; cd ..
     
     python3 soc/src/soc/decoder/power_decoder.py
     yosys -p "read_ilang decoder.il; show dec31" 
@@ -160,4 +160,7 @@ accelerated opcodes (all of which SwiftShader lacks)
 Also, individuals with experience in formal mathematical verification
 are quite welcome.
 
-# [Documentation](Documentation/SOC/index)
+# Documentation
+
+ - [Source Code](/Documentation/index)
+ - [Architecture](3d_gpu/architecture)