Enable LR/SC tests, even for uniprocessors

[riscv-tests.git] / isa / rv32ui / sb.S

diff --git a/isa/rv32ui/sb.S b/isa/rv32ui/sb.S
index 9d6830b52f13db1009441c61c8db56903a587789..05d1894f70bb81969b0dcf19013c35612e938088 100644 (file)
--- a/isa/rv32ui/sb.S
+++ b/isa/rv32ui/sb.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # sb.S
 #-----------------------------------------------------------------------------
@@ -17,13 +19,7 @@ RVTEST_CODE_BEGIN
 
   TEST_ST_OP( 2, lb, sb, 0xffffffaa, 0, tdat );
   TEST_ST_OP( 3, lb, sb, 0x00000000, 1, tdat );
-#ifdef __RISCVEL
   TEST_ST_OP( 4, lh, sb, 0xffffefa0, 2, tdat );
-#elif defined(__RISCVEB)
-#else
-  TEST_ST_OP( 4, lh, sb, 0xffffa0ef, 2, tdat );
-#error unknown endianness!
-#endif
   TEST_ST_OP( 5, lb, sb, 0x0000000a, 3, tdat );
 
   # Test with negative offset