Reset address translation/perms before PrivChange

[riscv-tests.git] / isa / rv64si / sbreak.S

diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S
index dbdf7ae22dcd68fcb9d82ad13c6fef201925f10d..31efff83910b4878dcca38fdc0a975bed64281db 100644 (file)
--- a/isa/rv64si/sbreak.S
+++ b/isa/rv64si/sbreak.S
@@ -13,25 +13,33 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define sret mret
+  #define stvec_handler mtvec_handler
+#endif
 
   li TESTNUM, 2
+
+do_break:
   sbreak
   j fail
 
-  j pass
-
   TEST_PASSFAIL
 
-stvec:
+  .align 2
+  .global stvec_handler
+stvec_handler:
   li t1, CAUSE_BREAKPOINT
   csrr t0, scause
   bne t0, t1, fail
+  la t1, do_break
   csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
+  bne t0, t1, fail
+  j pass
 
 RVTEST_CODE_END