+# See LICENSE for license details.
+
#*****************************************************************************
# ma_vld.S
#-----------------------------------------------------------------------------
RVTEST_RV64S
RVTEST_CODE_BEGIN
- mfpcr a3,cr0
- li a4,1
- slli a5,a4,8
- or a3,a3,a4 # enable traps
- mtpcr a3,cr0
+ li a0, SR_EA | SR_EI
+ csrs status, a0
la a3,handler
- mtpcr a3,cr3 # set exception handler
+ csrw evec,a3 # set exception handler
+
+ csrr a3,status
+ li a4,(1 << IRQ_COP)
+ slli a4,a4,SR_IM_SHIFT
+ or a3,a3,a4 # enable IM[COP]
+ csrw status,a3
vsetcfg 32,0
li a3,4
handler:
vxcptkill
- li x28,2
+ li TESTNUM,2
# check cause
- mfpcr a3,cr6
- li a4,28
+ vxcptcause a3
+ li a4,HWACHA_CAUSE_MISALIGNED_LOAD
bne a3,a4,fail
# check vec irq aux
- mfpcr a3,cr2
+ vxcptaux a3
la a4,dest+1
bne a3,a4,fail
ld a1,0(a5)
li a2,5
- li x28,2
+ li TESTNUM,2
bne a1,a2,fail
ld a1,8(a5)
- li x28,3
+ li TESTNUM,3
bne a1,a2,fail
ld a1,16(a5)
- li x28,4
+ li TESTNUM,4
bne a1,a2,fail
ld a1,24(a5)
- li x28,5
+ li TESTNUM,5
bne a1,a2,fail
TEST_PASSFAIL