+# See LICENSE for license details.
+
#*****************************************************************************
# ma_vt_inst.S
#-----------------------------------------------------------------------------
#include "riscv_test.h"
#include "test_macros.h"
-RVTEST_RV64S
+RVTEST_RV64SV
RVTEST_CODE_BEGIN
- li a0, SR_EA | SR_EI
- csrs status, a0
-
- la a3,handler
- csrw evec,a3
-
- csrr a3,status
- li a4,(1 << IRQ_COP)
- slli a4,a4,SR_IM_SHIFT
- or a3,a3,a4 # enable IM[COP]
- csrw status,a3
-
vsetcfg 32,0
li a3,4
vsetvl a3,a3
add x2,x2,x3
stop
-handler:
+stvec_handler:
vxcptkill
- li x28,2
+ li TESTNUM,2
# check cause
- vxcptcause a3
+ csrr a3, scause
li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
bne a3,a4,fail
# check badvaddr
- vxcptaux a3
+ csrr a3, sbadaddr
la a4,vtcode1+2
+ andi a3, a3, -4 # mask off lower bits so that may
+ andi a4, a4, -4 # ignore impl. specific behavior
bne a3,a4,fail
# make sure vector unit has cleared out
ld a1,0(a5)
li a2,5
- li x28,2
+ li TESTNUM,2
bne a1,a2,fail
ld a1,8(a5)
- li x28,3
+ li TESTNUM,3
bne a1,a2,fail
ld a1,16(a5)
- li x28,4
+ li TESTNUM,4
bne a1,a2,fail
ld a1,24(a5)
- li x28,5
+ li TESTNUM,5
bne a1,a2,fail
TEST_PASSFAIL