(no commit message)

[libreriscv.git] / isa_conflict_resolution / isamux_isans.mdwn

diff --git a/isa_conflict_resolution/isamux_isans.mdwn b/isa_conflict_resolution/isamux_isans.mdwn
index 70b0bee37f919a3e49c94167aca52e3f2dccb72b..4cf87261caabecaec40b2413fe06d6bafa325daf 100644 (file)
--- a/isa_conflict_resolution/isamux_isans.mdwn
+++ b/isa_conflict_resolution/isamux_isans.mdwn
@@ -3,8 +3,11 @@
 Links:
 
 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-February/004190.html>
+* bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=214>
 
-A fixed number of additional (hidden) bits, conceptually a "namespace", that go directly and non-optionally
+A fixed number of additional (hidden) bits, conceptually a "namespace",
+set by way of a CSR or other out-of-band mechanism,
+that go directly and non-optionally
 into the instruction decode phase, extending (in each implementation) the
 opcode length to 16+N, 32+N, 48+N, where N is a hard fixed quantity on
 a per-implementor basis.
@@ -52,7 +55,7 @@ RV Mode
 * in RV mode, bits 1 thru 5 provide up to 16 possible alternative meanings (namespaces) for 16 Bit opcodes. "pages" if you will. The top bit indicates custom meanings. When set to 0, the top bit is for official usage.
 * Bits 15 thru 23 are reserved.
 * Bits 24 thru 31 are for custom usage.
-* bit 6 ("B") is LE/BE
+* bit 6 ("B") is endian-selection: LE/BE
 
 16 bit page examples: