(no commit message)

[libreriscv.git] / isa_conflict_resolution / isamux_isans.mdwn

diff --git a/isa_conflict_resolution/isamux_isans.mdwn b/isa_conflict_resolution/isamux_isans.mdwn
index 5bd4a122a6afa02c8ce6231ae2c6167461f669ce..4cf87261caabecaec40b2413fe06d6bafa325daf 100644 (file)
--- a/isa_conflict_resolution/isamux_isans.mdwn
+++ b/isa_conflict_resolution/isamux_isans.mdwn
@@ -1,6 +1,13 @@
 # Note-form on ISAMUX (aka "ISANS")
 
-A fixed number of additional (hidden) bits, conceptually a "namespace", that go directly and non-optionally
+Links:
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-February/004190.html>
+* bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=214>
+
+A fixed number of additional (hidden) bits, conceptually a "namespace",
+set by way of a CSR or other out-of-band mechanism,
+that go directly and non-optionally
 into the instruction decode phase, extending (in each implementation) the
 opcode length to 16+N, 32+N, 48+N, where N is a hard fixed quantity on
 a per-implementor basis.
@@ -17,6 +24,16 @@ be relevant for a fixed number of instructions at a time.  Caveat:
 allowing such a countdown to cross branch-points is unwise (illegal
 instruction?)
 
+An example of a pre-existing "namespace" switch that has been in
+prevalent use for several decades (SPARC and other architectures):
+dynamic runtime selectability of littel-endian / big-endian "meaning"
+of instructions by way of a "mode switch" instruction (of some kind).
+
+That "switch" is in effect a 33rd (hidden) bit that is part of the opcode,
+going directly into the mux / decode phase of instruction decode, and
+thus qualifies categorically as a "namespace".  This proposal both formalises
+and generalises that concept.
+
 # Hypothetical Format
 
 Note that this is a hypothetical format, yet TBD, where particular attention
@@ -38,7 +55,7 @@ RV Mode
 * in RV mode, bits 1 thru 5 provide up to 16 possible alternative meanings (namespaces) for 16 Bit opcodes. "pages" if you will. The top bit indicates custom meanings. When set to 0, the top bit is for official usage.
 * Bits 15 thru 23 are reserved.
 * Bits 24 thru 31 are for custom usage.
-* bit 6 ("B") is LE/BE
+* bit 6 ("B") is endian-selection: LE/BE
 
 16 bit page examples: