ice40: split out cells_map.v into ff_map.v

[yosys.git] / kernel / bitpattern.h

diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h
index 00bbc3bfb50fdc7d6dbd58411f15bb8bdedf57c9..894a95ed1ff3ff22d714f2c8a081b6b72a6db817 100644 (file)
--- a/kernel/bitpattern.h
+++ b/kernel/bitpattern.h
@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -30,7 +30,7 @@ struct BitPatternPool
        int width;
        struct bits_t {
                std::vector<RTLIL::State> bitdata;
-               unsigned int cached_hash;
+               mutable unsigned int cached_hash;
                bits_t(int width = 0) : bitdata(width), cached_hash(0) { }
                RTLIL::State &operator[](int index) {
                        return bitdata[index];
@@ -45,7 +45,7 @@ struct BitPatternPool
                }
                unsigned int hash() const {
                        if (!cached_hash)
-                               ((bits_t*)this)->cached_hash = hash_ops<std::vector<RTLIL::State>>::hash(bitdata);
+                               cached_hash = hash_ops<std::vector<RTLIL::State>>::hash(bitdata);
                        return cached_hash;
                }
        };
@@ -154,7 +154,7 @@ struct BitPatternPool
        {
                return database.empty();
        }
-}; 
+};
 
 YOSYS_NAMESPACE_END