btor backend: add option to not include internal names

[yosys.git] / kernel / celledges.cc

diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index 54e0168e255f3bc61b6b100919e2f311907ef836..314e7c77e76c289798be74513f5e5fcb5361c9a9 100644 (file)
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -187,7 +187,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
                return true;
        }
 
-       // FIXME: $mul $div $mod $slice $concat
+       // FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
        // FIXME: $lut $sop $alu $lcu $macc $fa
 
        return false;