Add more options and time handling

[yosys.git] / kernel / celledges.cc

diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index 54e0168e255f3bc61b6b100919e2f311907ef836..af07d26b316c04e219b8f134b22e393e90a688b4 100644 (file)
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -187,7 +187,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
                return true;
        }
 
-       // FIXME: $mul $div $mod $slice $concat
+       // FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
        // FIXME: $lut $sop $alu $lcu $macc $fa
 
        return false;