ice40: split out cells_map.v into ff_map.v

[yosys.git] / kernel / celledges.h

diff --git a/kernel/celledges.h b/kernel/celledges.h
index fe863766ca6a1f482756cf7e54daf0458bd2d893..2cc297cb28c6abf6383329cc07b9ba250267d55c 100644 (file)
--- a/kernel/celledges.h
+++ b/kernel/celledges.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
@@ -28,8 +28,8 @@ YOSYS_NAMESPACE_BEGIN
 struct AbstractCellEdgesDatabase
 {
        virtual ~AbstractCellEdgesDatabase() { }
-       virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) = 0;
-       bool add_cell(RTLIL::Cell *cell);
+       virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;
+       bool add_edges_from_cell(RTLIL::Cell *cell);
 };
 
 struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
@@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
        dict<SigBit, pool<SigBit>> db;
        FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
 
-       virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override {
+       void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
                SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
                SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
                db[from_sigbit].insert(to_sigbit);
@@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
        dict<SigBit, pool<SigBit>> db;
        RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
 
-       virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override {
+       void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
                SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
                SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
                db[to_sigbit].insert(from_sigbit);