Merge branch 'koriakin/xc7nocarrymux' into xaig

[yosys.git] / kernel / consteval.h

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 4d48b45eaee4566da7769fb4affd0fa2b0818f3c..154373a8deeef29bb2223ae6029d4ffeb167a31c 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -36,8 +36,9 @@ struct ConstEval
        SigSet<RTLIL::Cell*> sig2driver;
        std::set<RTLIL::Cell*> busy;
        std::vector<SigMap> stack;
+       RTLIL::State defaultval;
 
-       ConstEval(RTLIL::Module *module) : module(module), assign_map(module)
+       ConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)
        {
                CellTypes ct;
                ct.setup_internals();
@@ -320,8 +321,13 @@ struct ConstEval
                        if (sig_d.size() > 0 && !eval(sig_d, undef, cell))
                                return false;
 
-                       set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(),
-                                       sig_c.as_const(), sig_d.as_const()));
+                       bool eval_err = false;
+                       RTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);
+
+                       if (eval_err)
+                               return false;
+
+                       set(sig_y, eval_ret);
                }
 
                return true;
@@ -365,6 +371,12 @@ struct ConstEval
                if (sig.is_fully_const())
                        return true;
 
+               if (defaultval != RTLIL::State::Sm) {
+                       for (auto &bit : sig)
+                               if (bit.wire) bit = defaultval;
+                       return true;
+               }
+
                for (auto &c : sig.chunks())
                        if (c.wire != NULL)
                                undef.append(c);