Refactoring: Renamed RTLIL::Module::cells to cells_

[yosys.git] / kernel / consteval.h

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 10116ccfec9e8095046e88ffc35bc7467405d240..1727d91cf51dd6a91593a9db52b70aba8c25a5df 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -40,10 +40,10 @@ struct ConstEval
                ct.setup_internals();
                ct.setup_stdcells();
 
-               for (auto &it : module->cells) {
+               for (auto &it : module->cells_) {
                        if (!ct.cell_known(it.second->type))
                                continue;
-                       for (auto &it2 : it.second->connections)
+                       for (auto &it2 : it.second->connections())
                                if (ct.cell_output(it.second->type, it2.first))
                                        sig2driver.insert(assign_map(it2.second), it.second);
                }
@@ -71,11 +71,8 @@ struct ConstEval
                assign_map.apply(sig);
 #ifndef NDEBUG
                RTLIL::SigSpec current_val = values_map(sig);
-               current_val.expand();
-               for (size_t i = 0; i < current_val.chunks.size(); i++) {
-                       RTLIL::SigChunk &chunk = current_val.chunks[i];
-                       assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]);
-               }
+               for (int i = 0; i < SIZE(current_val); i++)
+                       assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
 #endif
                values_map.add(sig, RTLIL::SigSpec(value));
        }
@@ -90,22 +87,22 @@ struct ConstEval
        {
                RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-               assert(cell->connections.count("\\Y") > 0);
-               sig_y = values_map(assign_map(cell->connections["\\Y"]));
+               assert(cell->has("\\Y"));
+               sig_y = values_map(assign_map(cell->get("\\Y")));
                if (sig_y.is_fully_const())
                        return true;
 
-               if (cell->connections.count("\\S") > 0) {
-                       sig_s = cell->connections["\\S"];
+               if (cell->has("\\S")) {
+                       sig_s = cell->get("\\S");
                        if (!eval(sig_s, undef, cell))
                                return false;
                }
 
-               if (cell->connections.count("\\A") > 0)
-                       sig_a = cell->connections["\\A"];
+               if (cell->has("\\A"))
+                       sig_a = cell->get("\\A");
 
-               if (cell->connections.count("\\B") > 0)
-                       sig_b = cell->connections["\\B"];
+               if (cell->has("\\B"))
+                       sig_b = cell->get("\\B");
 
                if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")
                {
@@ -113,10 +110,10 @@ struct ConstEval
                        int count_maybe_set_s_bits = 0;
                        int count_set_s_bits = 0;
 
-                       for (int i = 0; i < sig_s.width; i++)
+                       for (int i = 0; i < sig_s.size(); i++)
                        {
                                RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
-                               RTLIL::SigSpec b_slice = sig_b.extract(sig_y.width*i, sig_y.width);
+                               RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());
 
                                if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
                                        y_candidates.push_back(b_slice);
@@ -162,9 +159,9 @@ struct ConstEval
                }
                else
                {
-                       if (sig_a.width > 0 && !eval(sig_a, undef, cell))
+                       if (sig_a.size() > 0 && !eval(sig_a, undef, cell))
                                return false;
-                       if (sig_b.width > 0 && !eval(sig_b, undef, cell))
+                       if (sig_b.size() > 0 && !eval(sig_b, undef, cell))
                                return false;
                        set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const()));
                }
@@ -210,9 +207,9 @@ struct ConstEval
                if (sig.is_fully_const())
                        return true;
 
-               for (size_t i = 0; i < sig.chunks.size(); i++)
-                       if (sig.chunks[i].wire != NULL)
-                               undef.append(sig.chunks[i]);
+               for (auto &c : sig.chunks())
+                       if (c.wire != NULL)
+                               undef.append(c);
                return false;
        }