Refactoring: Renamed RTLIL::Module::cells to cells_
[yosys.git] / kernel / consteval.h
index 4050d2dcf929cd5c565f6c6984c8a6c06b1484c3..1727d91cf51dd6a91593a9db52b70aba8c25a5df 100644 (file)
@@ -40,7 +40,7 @@ struct ConstEval
                ct.setup_internals();
                ct.setup_stdcells();
 
-               for (auto &it : module->cells) {
+               for (auto &it : module->cells_) {
                        if (!ct.cell_known(it.second->type))
                                continue;
                        for (auto &it2 : it.second->connections())
@@ -87,21 +87,21 @@ struct ConstEval
        {
                RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-               assert(cell->connections().count("\\Y") > 0);
+               assert(cell->has("\\Y"));
                sig_y = values_map(assign_map(cell->get("\\Y")));
                if (sig_y.is_fully_const())
                        return true;
 
-               if (cell->connections().count("\\S") > 0) {
+               if (cell->has("\\S")) {
                        sig_s = cell->get("\\S");
                        if (!eval(sig_s, undef, cell))
                                return false;
                }
 
-               if (cell->connections().count("\\A") > 0)
+               if (cell->has("\\A"))
                        sig_a = cell->get("\\A");
 
-               if (cell->connections().count("\\B") > 0)
+               if (cell->has("\\B"))
                        sig_b = cell->get("\\B");
 
                if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")