ct.setup_internals();
ct.setup_stdcells();
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
continue;
- for (auto &it2 : it.second->connections)
+ for (auto &it2 : it.second->connections())
if (ct.cell_output(it.second->type, it2.first))
sig2driver.insert(assign_map(it2.second), it.second);
}
{
RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
- assert(cell->connections.count("\\Y") > 0);
- sig_y = values_map(assign_map(cell->connections["\\Y"]));
+ assert(cell->has("\\Y"));
+ sig_y = values_map(assign_map(cell->get("\\Y")));
if (sig_y.is_fully_const())
return true;
- if (cell->connections.count("\\S") > 0) {
- sig_s = cell->connections["\\S"];
+ if (cell->has("\\S")) {
+ sig_s = cell->get("\\S");
if (!eval(sig_s, undef, cell))
return false;
}
- if (cell->connections.count("\\A") > 0)
- sig_a = cell->connections["\\A"];
+ if (cell->has("\\A"))
+ sig_a = cell->get("\\A");
- if (cell->connections.count("\\B") > 0)
- sig_b = cell->connections["\\B"];
+ if (cell->has("\\B"))
+ sig_b = cell->get("\\B");
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")
{